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| 19-3454; Rev 0; 11/04 Stereo Audio DAC with DirectDrive Headphone Amplifier General Description The MAX9850 is a low-power, high-performance stereo audio DAC with an integrated DirectDriveTM headphone amplifier. The MAX9850 is designed to meet the board space and performance requirements of portable devices such as cell phones and MP3 and portable DVD players. The MAX9850 uses Maxim's patented DirectDrive headphone technology that produces a ground-biased analog audio output from a single supply, which allows for driving the headphones directly from the amplifier outputs without large DC-blocking capacitors. This feature saves board space, provides higher click/pop suppression, and improves low-frequency (bass) response. The architecture does not require the headphone jack to be biased to a DC voltage and thus allows for a conventional, grounded chassis design. The MAX9850's flexible clocking circuitry utilizes any available system clock up to 40MHz, eliminating the need for an external PLL and multiple crystal oscillators. The DAC supports a wide range of sample rates from 8kHz to 48kHz in both master and slave modes, making the MAX9850 the easiest to use and most versatile audio DAC available. It can also be operated like traditional synchronous DACs, at any integer-oversampling ratio. The audio DAC receives input data over a flexible 3-wire interface that supports up to 32 bits of left-justified, right-justified, or I2S-compatible audio data. Stereo audio line inputs are provided to either mix analog audio with the digital input stream, or to drive the headphone outputs directly. Mode settings, headphone amplifier volume controls, and shutdown for both the headphone and line outputs are programmed through a 2-wire, I2C-compatible interface. The MAX9850 is fully specified over the -40C to +85C extended temperature range and is available in a lowprofile, 28-pin thin QFN package (5mm x 5mm x 0.8mm). Features 1.8V to 3.6V Single-Supply Operation 30mW Stereo Headphone Output Power with 1.8V Supply DirectDrive Outputs Eliminate DC-Blocking Capacitors 91dB PSRR at 1kHz Any Master Clock Up to 40MHz Flexible I2S-Compatible Digital Audio Interface I2C Headphone Volume and Mute Control Stereo Line Inputs and Outputs Clickless/Popless Operation 2-Wire (I2C)-Compatible Control Interface Available in 28-Pin Thin QFN Package MAX9850 Ordering Information PART MAX9850ETI TEMP RANGE -40C to +85C PIN-PACKAGE 28 Thin QFN-EP* *EP = Exposed Paddle. Package code T2855-6 (see Package Information section). Pin Configuration appears at end of data sheet. Block Diagram MCLK 1.8V TO 3.6V INR Applications MP3/Portable Multimedia Players Cell Phones/Smart Phones Portable DVD Players Purchase of I2C components from Maxim Integrated Products, Inc. or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. SDIN BCLK LRCLK SDA SCL ADD GPIO DIGITAL PLL MAX9850 DAC OUTR LINE OUT DIGITAL AUDIO DAC + + INL HPR HPL OUTL I2C LINE OUT ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. Stereo Audio DAC with DirectDrive Headphone Amplifier MAX9850 ABSOLUTE MAXIMUM RATINGS (Voltages with respect to AGND.) DVDD, AVDD, PVDD ..................................................-0.3V to +4V AVDD Referenced to PVDD ....................................-0.3V to +0.3V SVSS, PVSS ...............................................................-4V to +0.3V SVSS Referenced to PVSS .....................................-0.3V to +0.3V DGND, PGND........................................................-0.3V to +0.3V BCLK, LRCLK, HPS, SDIN.......................-0.3V to (DVDD + 0.3V) GPIO, MCLK.............................................................-0.3V to +4V REF, PREG ...............................................-0.3V to (AVDD + 0.3V) NREG ........................................................+0.3V to (SVSS - 0.3V) SDA, SCL, ADD ........................................................-0.3V to +4V INL, INR .......................................................................-2V to +2V HPR, HPL.....................................(SVSS - 0.3V) to (AVDD + 0.3V) OUTL, OUTR .............................(NREG - 0.3V) to (PREG + 0.3V) C1N ............................................(PVSS - 0.3V) to (PGND + 0.3V) C1P ............................................(PGND - 0.3V) to (PVDD + 0.3V) Current Into/Out of Any Pin ...............................................100mA Duration of HPL, HPR, OUTL, OUTR Short Circuit to AGND .................................Continuous Continuous Power Dissipation (TA = +70C) 28-Pin Thin QFN (derate 35.7mW/C above +70C) .....2857mW Junction Temperature ......................................................+150C Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (DVDD = AVDD = PVDD = 3.0V, AGND = DGND = PGND = 0V, C1 = 0.47F, C2 = 2.2F, CNREG = CPREG = CREF = 1F to AGND, RLOAD_HP = 32 to AGND, RLOAD_OUT = 10k to AGND, fLRCLK = 48kHz, fMCLK = 12.288MHz, volume set to -9.5dB, TA = TMIN to TMAX, unless otherwise noted. Typical specifications at TA = +25C, unless otherwise noted.) PARAMETER Analog Supply Voltage Digital Supply Voltage SYMBOL AVDD, PVDD DVDD Full operation (Note 1), no headphone or line output load Full operation (Note 1), headphones disabled Digital Supply Current Analog Shutdown Current Digital Shutdown Current Shutdown to Full Operation (Note 1) Power-On to Full Operation (Note 1) 0dBFS Output Voltage Dynamic Range (Note 3) DIDD AISHDN DISHDN tON tPON Full operation (Note 1), no line output load AVDD = 1.8V AVDD = 3.0V AVDD = 1.8V AVDD = 3.0V DVDD = 1.8V DVDD = 3.0V AVDD = PVDD CONDITIONS MIN 1.8 1.8 5.5 5.9 3.5 3.75 2.1 3.8 1.5 0.3 1.3 1.4 10 5 2.8 mA A A ms ms 5.3 TYP MAX 3.6 3.6 7.7 mA UNITS V V Analog Supply Current AIDD IAVDD + IPVDD, AVDD = PVDD = 1.8V Static digital interface, DVDD = 1.8V DAC PERFORMANCE/LINE OUTPUTS (Note 2) VOUT_FS DR AVDD = 3.0V AVDD = 1.8V Unweighted Signal-to-Noise Ratio (Note 4) SNR A-weighted AVDD = 1.8V, unweighted AVDD = 1.8V, A-weighted 82 1.85 1.95 87.5 87.5 88 91 88 91 dB 2.05 VP-P dB 2 _______________________________________________________________________________________ Stereo Audio DAC with DirectDrive Headphone Amplifier ELECTRICAL CHARACTERISTICS (continued) (DVDD = AVDD = PVDD = 3.0V, AGND = DGND = PGND = 0V, C1 = 0.47F, C2 = 2.2F, CNREG = CPREG = CREF = 1F to AGND, RLOAD_HP = 32 to AGND, RLOAD_OUT = 10k to AGND, fLRCLK = 48kHz, fMCLK = 12.288MHz, volume set to -9.5dB, TA = TMIN to TMAX, unless otherwise noted. Typical specifications at TA = +25C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS 0dBFS -60dBFS Total Harmonic Distortion Plus Noise THD+N fIN = 984.375Hz AVDD = 1.8V, 0dBFS AVDD = 1.8V, -60dBFS Line Output Offset Voltage Channel-to-Channel Gain Matching VOS_LINE AV/AV OUTL to OUTR, OUTR to OUTL VRIPPLE = 100mVP-P, fIN = 1kHz, applied to AVDD and PVDD VRIPPLE = 100mVP-P, fIN = 20kHz, applied to AVDD and PVDD Crosstalk Sampling Frequency Range MCLK Frequency DAC 8x INTERPOLATION FILTER Passband Frequency Frequency Response Stopband Attenuation Stopband Frequency LINE INPUTS (INL, INR) Line Input Voltage IN_ to OUT_ Gain Line Input Bias Voltage INL and INR Input Resistance PREG Output Voltage NREG Output Voltage REF Output Voltage VIN_LINE AV_LINE VBIAS_LINE RIN_LINE VPREG VNREG VREF -1 -1.05 -10 10 -1 0 22 1.60 -1.15 1.23 +1 -0.95 +10 V V/V mV k V V V PB FR SBA SB Attenuation greater than SBA To -1dB corner 10Hz to 20kHz 0 -0.1 58 0.58 x fS 7.42 x fS 0.48 x fS +0.1 kHz dB dB kHz XTALK fS fMCLK fOUT = 1kHz, VOUT = 2VP-P (OUTL to OUTR) or (OUTR to OUTL) 8 8.448 -10 MIN TYP 87 27.5 -81 -27.5 0 0.04 87 dB 67 -105 48 40 dB kHz MHz -22 +14 mV dB dB MAX UNITS MAX9850 Power-Supply Rejection Ratio PSRR INTERNAL REGULATORS (NREG, PREG) _______________________________________________________________________________________ 3 Stereo Audio DAC with DirectDrive Headphone Amplifier MAX9850 ELECTRICAL CHARACTERISTICS (continued) (DVDD = AVDD = PVDD = 3.0V, AGND = DGND = PGND = 0V, C1 = 0.47F, C2 = 2.2F, CNREG = CPREG = CREF = 1F to AGND, RLOAD_HP = 32 to AGND, RLOAD_OUT = 10k to AGND, fLRCLK = 48kHz, fMCLK = 12.288MHz, volume set to -9.5dB, TA = TMIN to TMAX, unless otherwise noted. Typical specifications at TA = +25C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS RL = 16 AVDD = 3.0V THD+N = 1% fIN = 1kHz, headphone volume = +6dB RL = 32 AVDD = 3.0V RL = 16 AVDD = 1.8V RL = 32 AVDD = 1.8V Full-Scale Headphone Amplifier Output Voltage Line In to HP Output Voltage Gain Total Harmonic Distortion Plus Noise VOUT_FS AV_HP THD+N Volume = +5dB, HP unloaded Volume = +3dB, HP unloaded RL = 32, POUT = 60mW, fIN = 1kHz RL = 16, POUT = 60mW, fIN = 1kHz Unweighted Signal-to-Noise Ratio (Note 5) SNR A-weighted AVDD = 1.8V, unweighted AVDD = 1.8V, A-weighted VRIPPLE = 100mVP-P, frequency = 1kHz, applied to AVDD and PVDD VRIPPLE = 100mVP-P, frequency = 20kHz, applied to AVDD and PVDD Headphone Output Offset Voltage Slew Rate Maximum Capacitive Load Crosstalk Channel-to-Channel Gain Matching Internal Charge-Pump Oscillator Frequency Charge-Pump Operating Frequency Range Volume Control Range VOS_HP SR CL XTALK AV/AV fCP Charge-pump clock derived from MCLK 550 550 -73.5 No sustained oscillations RHP = 32, POUT = 3.5mW, fIN = 1kHz (HPL to HPR) or (HPR to HPL) Volume = -11.5dB -20 15 1.16 1.34 40 MIN TYP MAX UNITS HEADPHONE OUTPUTS (HPL, HPR) 95 65 mW 30 25 1.23 1.41 -94 -90 88 90 88 91 91 dB 72 0 0.47 150 -85 0.05 667 775 775 +6.0 +20 mV V/s pF dB dB kHz kHz dB dB 1.30 1.48 VRMS V/V dB Output Power OUT Power-Supply Rejection Ratio PSRR 4 _______________________________________________________________________________________ Stereo Audio DAC with DirectDrive Headphone Amplifier ELECTRICAL CHARACTERISTICS (continued) (DVDD = AVDD = PVDD = 3.0V, AGND = DGND = PGND = 0V, C1 = 0.47F, C2 = 2.2F, CNREG = CPREG = CREF = 1F to AGND, RLOAD_HP = 32 to AGND, RLOAD_OUT = 10k to AGND, fLRCLK = 48kHz, fMCLK = 12.288MHz, volume set to -9.5dB, TA = TMIN to TMAX, unless otherwise noted. Typical specifications at TA = +25C, unless otherwise noted.) PARAMETER Mute Attenuation DIGITAL INPUTS (GPIO, SCL, SDA, BCLK, LRCLK, SDIN, ADD, MCLK) Input High Voltage Input Low Voltage Input Leakage Current Input Hysteresis Input Capacitance Output-High Leakage Current Output Low Voltage CIN IOH VOL VOH = DVDD (Note 6) DVDD > 2V IOL = 3mA DVDD < 2V VIH VIL IIH, IIL VIH = DVDD, VIL = DGND -10 0.09 x DVDD 10 1 0.4 0.2 x DVDD DVDD 0.4 0.4 0.7 x DVDD 0.25 x DVDD Full shutdown, VIH = DVDD Normal operation, VIH = DVDD Full shutdown, VIL = DGND Normal operation, VIL = DGND 0.05 x DVDD 400 1 1 100 V 0.8 x DVDD 0.2 x DVDD +10 V V A V pF A SYMBOL CONDITIONS MIN TYP 100 MAX UNITS dB MAX9850 OPEN-DRAIN DIGITAL OUTPUTS (GPIO, SDA) CMOS DIGITAL OUTPUTS (BCLK, LRCLK) Output High Voltage Output Low Voltage HEADPHONE SENSE INPUT (HPS) Input High Voltage Input Low Voltage Input-High Leakage Current Input-Low Leakage Current Input Hysteresis VIH VIL IIH IIL V V A A V VOH VOL IOH = 1mA IOL = 1mA V V _______________________________________________________________________________________ 5 Stereo Audio DAC with DirectDrive Headphone Amplifier MAX9850 TIMING CHARACTERISTICS (DVDD = AVDD = PVDD = 3.0V, AGND = DGND = PGND = 0V, C1 = 0.47F, C2 = 2.2F, CNREG = CPREG = CREF = 1F to AGND, RLOAD_HP = 32 to AGND, RLOAD_LINE = 10k to AGND, fLRCLK = 48kHz, fMCLK = 12.288MHz, volume set to -9.5dB, TA = TMIN to TMAX, unless otherwise noted. Typical specifications at TA = +25C, unless otherwise noted.) PARAMETER I2C TIMING Serial Clock Frequency Bus Free Time Between STOP and START Conditions Hold Time (Repeated) START Condition SCL Pulse-Width Low SCL Pulse-Width High Repeated START Condition Setup Time Data Hold Time Data Setup Time Bus Capacitance SDA and SCL Receiving Rise Time (Note 7) SDA and SCL Receiving Fall Time (Note 7) SDA Transmitting Fall Time (Note 7) Setup Time for STOP Condition Pulse Width of Suppressed Spike DIGITAL AUDIO TIMING BCLK Period (Note 8) Low or High BCLK Pulse Width BCLK and LRCLK Rise Time BCLK and LRCLK Fall Time SDIN or LRCLK to BCLK Rising Setup Time SDIN or LRCLK to BCLK Rising Hold Time tBCLK tBCLK_PW tR tF tDBSU, tBWSU tDBH, tBWBH DVDD = 1.8V DVDD = 3.6V Master mode, CLOAD = 15pF Master mode, CLOAD = 15pF 30 0 5 3x 1 / fICLK 0.35 x tBCLK 1 1 ns ns ns ns ns ns fSCL tBUF tHD, STA tLOW tHIGH tSU, STA tHD, DAT tSU, DAT CB tR tF DVDD = 1.8V tF DVDD = 3.6V tSU, STO tSP 20 + 0.1CB 20 + 0.1CB 20 + 0.1CB 20 + 0.05CB 0.6 0 0 1.3 0.6 1.3 0.6 0.6 0 100 400 300 300 250 ns 250 s 50 ns 900 400 kHz s s s s s ns ns pF ns ns SYMBOL CONDITIONS MIN TYP MAX UNITS Note 1: Full operation is defined as clocking all zeros into the DAC while the DAC, headphone outputs, and line outputs are all enabled. Note 2: DAC performance specifications measured using the line outputs, OUTL and OUTR. Note 3: Dynamic range is defined as the SNR of a 1kHz, -60dBFS input signal measured with an A-weighted filter, then normalized to full scale (+60dB). Note 4: DAC SNR measured from DAC inputs to OUTL and OUTR. 6 _______________________________________________________________________________________ Stereo Audio DAC with DirectDrive Headphone Amplifier MAX9850 Note 5: Note 6: Note 7: Note 8: Headphone amplifier SNR measured from line inputs to headphone outputs. GPIO is 100k to ground when DVDD < VOH < 3.6V. CB is in pF. fICLK derived by dividing fMCLK by 1, 2, 3, or 4. See the Registers and Bit Descriptions section. TYPICAL POWER DISSIPATION AT AVDD = 1.8V (No Headphone/Line Output Load) MODE Full Operation (Note 1) DAC to Line Outputs, Headphones Disabled Line Inputs to Line Outputs and Headphone Outputs, DAC Disabled Line Inputs to Line Outputs, DAC and Headphones Disabled Full Shutdown AVDD POWER 4.93mW 3.11mW 3.22mW 1.39mW 2.7W DVDD POWER 3.76mW 3.76mW 0.085mW 0.085mW 0.5W PVDD POWER 5.00mW 3.22mW 3.40mW 1.61mW <0.1W TOTAL POWER 13.70mW 10.10mW 6.71mW 3.08mW 3.2W Typical Operating Characteristics (DVDD = AVDD = PVDD = 3.0V, AGND = DGND = PGND = 0V, C1 = 0.47F, C2 = 2.2F, CNREG = CPREG = CREF = 1F, fS = 48kHz, fMCLK = 12.288MHz, master integer mode, headphone volume set to +6dB, both channels driven in-phase, TA = +25C, unless otherwise noted. fIN = 984.375Hz, A-weighted THD+N.) TOTAL HARMONIC DISTORTION PLUS NOISE (DAC TO HP) vs. POWER OUT MAX9850toc01 TOTAL HARMONIC DISTORTION PLUS NOISE (LINE IN TO HP) vs. POWER OUT MAX9850toc02 TOTAL HARMONIC DISTORTION PLUS NOISE (DAC TO HP) vs. POWER OUT AVDD = 1.8V RL = 32 1 MAX9850toc03 10 AVDD = 1.8V RL = 16 1 fIN = 1kHz 10 AVDD = 1.8V RL = 16 1 fIN = 1kHz THD+N (%) 10 fIN = 1kHz THD+N (%) 0.1 fIN = 10kHz 0.1 THD+N (%) fIN = 10kHz 0.1 fIN = 20Hz 0.01 fIN = 10kHz 0.01 fIN = 20Hz 0.001 0 10 20 30 40 50 60 POWER OUT (mW) 0.01 fIN = 20Hz 0.001 0 10 20 30 40 50 60 POWER OUT (mW) 0.001 0 10 20 30 40 50 POWER OUT (mW) _______________________________________________________________________________________ 7 Stereo Audio DAC with DirectDrive Headphone Amplifier MAX9850 Typical Operating Characteristics (continued) (DVDD = AVDD = PVDD = 3.0V, AGND = DGND = PGND = 0V, C1 = 0.47F, C2 = 2.2F, CNREG = CPREG = CREF = 1F, fS = 48kHz, fMCLK = 12.288MHz, master integer mode, headphone volume set to +6dB, both channels driven in-phase, TA = +25C, unless otherwise noted. fIN = 984.375Hz, A-weighted THD+N.) TOTAL HARMONIC DISTORTION PLUS NOISE (LINE IN TO HP) vs. POWER OUT MAX9850toc04 TOTAL HARMONIC DISTORTION PLUS NOISE (DAC TO HP) vs. POWER OUT MAX9850toc05 TOTAL HARMONIC DISTORTION PLUS NOISE (LINE IN TO HP) vs. POWER OUT AVDD = 3.0V RL = 16 fIN = 1kHz 1 THD+N (%) MAX9850toc06 10 AVDD = 1.8V RL = 32 1 THD+N (%) fIN = 1kHz 0.1 10 AVDD = 3.0V RL = 16 1 THD+N (%) fIN = 1kHz 0.1 fIN = 10kHz 10 fIN = 20Hz 0.1 fIN = 10kHz 0.01 0.01 fIN = 10kHz 0.01 fIN = 20Hz 0.001 50 0 20 40 60 80 100 POWER OUT (mW) 0.001 0 10 20 30 fIN = 20Hz 40 0.001 0 20 40 60 80 100 POWER OUT (mW) POWER OUT (mW) TOTAL HARMONIC DISTORTION PLUS NOISE (DAC TO HP) vs. POWER OUT MAX9850toc07 TOTAL HARMONIC DISTORTION PLUS NOISE (LINE IN TO HP) vs. POWER OUT MAX9850toc08 TOTAL HARMONIC DISTORTION PLUS NOISE (DAC TO HP) vs. FREQUENCY AVDD = 1.8V RL = 16 1 THD+N (%) MAX9850toc09 10 AVDD = 3.0V RL = 32 1 THD+N (%) fIN = 1kHz fIN = 10kHz 0.1 10 AVDD = 3.0V RL = 32 1 THD+N (%) 10 0.1 fIN = 1kHz fIN = 10kHz fIN = 20Hz 0.1 POUT = 5mW 0.01 fIN = 20Hz 0.001 0 20 40 60 80 100 POWER OUT (mW) 0.01 0.01 POUT = 21mW 0.001 0 20 40 60 80 100 POWER OUT (mW) 0.001 10 100 1k FREQUENCY (Hz) 10k 100k TOTAL HARMONIC DISTORTION PLUS NOISE (DAC TO HP) vs. FREQUENCY MAX9850toc10 TOTAL HARMONIC DISTORTION PLUS NOISE (DAC TO LINE OUT) vs. FREQUENCY MAX9850toc11 TOTAL HARMONIC DISTORTION PLUS NOISE (DAC TO HP) vs. FREQUENCY AVDD = 3.0V RL = 16 1 THD+N (%) POUT = 10mW 0.1 MAX9850toc12 10 AVDD = 1.8V RL = 32 1 THD+N (%) 10 AVDD = 1.8V TO 3.0V RL = 10k 1 THD+N (%) 10 0.1 POUT = 3mW 0.1 0.01 POUT = 15mW 0.001 10 100 1k FREQUENCY (Hz) 10k 100k 0.01 VOUT = 2VP-P 0.01 POUT = 60mW 0.001 10 100 1k FREQUENCY (Hz) 10k 100k 0.001 10 100 1k FREQUENCY (Hz) 10k 100k 8 _______________________________________________________________________________________ Stereo Audio DAC with DirectDrive Headphone Amplifier MAX9850 Typical Operating Characteristics (continued) (DVDD = AVDD = PVDD = 3.0V, AGND = DGND = PGND = 0V, C1 = 0.47F, C2 = 2.2F, CNREG = CPREG = CREF = 1F, fS = 48kHz, fMCLK = 12.288MHz, master integer mode, headphone volume set to +6dB, both channels driven in-phase, TA = +25C, unless otherwise noted. fIN = 984.375Hz, A-weighted THD+N.) TOTAL HARMONIC DISTORTION PLUS NOISE (DAC TO HP) vs. FREQUENCY MAX9850toc13 POWER DISSIPATION vs. POWER OUT MAX9850toc14 POWER DISSIPATION vs. POWER OUT AVDD = PVDD = DVDD = 3.0V POUT = PHPR + PHPL RLOAD = 16 MAX9850toc15 10 AVDD = 3.0V RL = 32 1 THD+N (%) 160 140 POWER DISSIPATION (mW) 120 100 80 60 40 20 0 RLOAD = 32 RLOAD = 16 AVDD = PVDD = DVDD = 1.8V POUT = PHPR + PHPL 350 300 POWER DISSIPATION (mW) 250 200 150 100 RLOAD = 32 50 0 0.1 POUT = 6mW 0.01 POUT = 50mW 0.001 10 100 1k FREQUENCY (Hz) 10k 100k 0 10 20 POWER OUT (mW) 30 40 0 50 100 150 POWER OUT (mW) POWER OUT vs. HEADPHONE LOAD MAX9850toc16 POWER OUT vs. HEADPHONE LOAD MAX9850toc17 POWER OUT vs. SUPPLY VOLTAGE 160 140 POWER OUT (mW) 120 100 80 60 40 THD+N = 1% RL = 16 LINE IN TO HP OUT fIN = 1kHz THD+N = 10% MAX9850toc18 50 45 40 POWER OUT (mW) 35 30 25 20 15 10 5 0 10 100 RLOAD () THD+N = 1% THD+N = 10% AVDD = 1.8V LINE IN TO HP OUT fIN = 1kHz 140 120 POWER OUT (mW) 100 THD+N = 10% 80 60 40 20 0 THD+N = 1% AVDD = 3.0V LINE IN TO HP OUT fIN = 1kHz 180 20 0 10 100 RLOAD () 1000 1.0 1.5 2.0 2.5 3.0 3.5 4.0 SUPPLY VOLTAGE (V) 1000 POWER OUT vs. SUPPLY VOLTAGE MAX9850toc19 POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (DAC TO HP) MAX9850toc20 POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (DAC TO LINE OUT) -10 -20 -30 -40 PSRR (dB) -50 -60 -70 -80 -90 -100 -110 -120 10 100 1k FREQUENCY (Hz) 10k 100k AVDD = 3.0VDC AVDD = 1.8VDC RLOAD = 10k VRIPPLE APPLIED TO AVDD AND PVDD = 100mVP-P CLOCKING ZEROS INTO DAC MAX9850toc21 100 90 80 POWER OUT (mW) 70 RL = 32 LINE IN TO HP OUT fIN = 1kHz 0 -10 -20 -30 -40 PSRR (dB) RLOAD = 10k VRIPPLE APPLIED TO AVDD AND PVDD = 100mVP-P CLOCKING ZEROS INTO DAC VOLUME SET AT -9.5dB 0 60 50 40 30 20 10 0 1.0 THD+N = 10% THD+N = 1% -50 -60 -70 -80 -90 -100 -110 -120 AVDD = 1.8VDC 10 100 1k FREQUENCY (Hz) 10k 100k AVDD = 3.0VDC 1.5 2.0 2.5 3.0 3.5 4.0 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 9 Stereo Audio DAC with DirectDrive Headphone Amplifier MAX9850 Typical Operating Characteristics (continued) (DVDD = AVDD = PVDD = 3.0V, AGND = DGND = PGND = 0V, C1 = 0.47F, C2 = 2.2F, CNREG = CPREG = CREF = 1F, fS = 48kHz, fMCLK = 12.288MHz, master integer mode, headphone volume set to +6dB, both channels driven in-phase, TA = +25C, unless otherwise noted. fIN = 984.375Hz, A-weighted THD+N.) CROSSTALK vs. FREQUENCY (DAC IN TO HP OUT) MAX9850toc22 CROSSTALK vs. FREQUENCY (LINE IN TO HP OUT) MAX9850toc23 CROSSTALK vs. FREQUENCY (DAC IN TO LINE OUT) -50 -60 VOLUME SET TO -9.5dB DAC IN = 0dBFS MAX9850toc24 -40 -50 -60 CROSSTALK (dB) VOLUME SET TO -9.5dB DAC IN = 0dBFS RLOAD = 32 L TO R -40 -50 -60 CROSSTALK (dB) -70 -80 -90 -100 -110 -120 R TO L L TO R VOLUME SET TO -9.5dB LINE IN = 1VRMS RLOAD = 32 -40 -70 -80 -90 CROSSTALK (dB) -70 -80 -90 -100 -110 -120 R TO L L TO R R TO L -100 -110 -120 10 100 1k FREQUENCY (Hz) 10k 100k 10 100 1k FREQUENCY (Hz) 10k 100k 10 100 1k FREQUENCY (Hz) 10k 100k FFT, SLAVE NONINTEGER MODE (DAC IN = 0dBFS) MAX9850toc25 FFT, SLAVE NONINTEGER MODE (DAC IN = -60dBFS) MAX9850toc26 FFT, SLAVE NONINTEGER MODE (DAC IN = IDLE) LINE OUT fMCLK = 12MHz MAX9850toc27 0 -20 -40 LINE OUT (dBFS) -60 -80 -100 -120 -140 0 5 LINE OUT fIN = 1kHz fMCLK = 12MHz 0 -20 -40 LINE OUT (dBFS) -60 -80 -100 -120 -140 LINE OUT fIN = 1kHz fMCLK = 12MHz 0 -20 -40 LINE OUT (dBFS) -60 -80 -100 -120 -140 10 15 FREQUENCY (kHz) 20 0 5 10 15 FREQUENCY (kHz) 20 0 5 10 15 FREQUENCY (Hz) 20 FFT, MASTER INTEGER MODE (DAC IN = 0dBFS) MAX9850toc28 FFT, MASTER INTEGER MODE (DAC IN = -60dBFS) MAX9850toc29 FFT, MASTER INTEGER MODE (DAC IN = IDLE) LINE OUT fMCLK = 12.288MHz MAX9850toc30 0 -20 -40 LINE OUT fIN = 1kHz fMCLK = 12.288MHz 0 -20 -40 LINE OUT (dBFS) -60 -80 -100 -120 -140 LINE OUT fIN = 1kHz fMCLK = 12.288MHz 0 -20 -40 LINE OUT (dBFS) -60 -80 -100 -120 -140 LINE OUT (dBFS) -60 -80 -100 -120 -140 0 5 10 15 FREQUENCY (Hz) 20 0 5 10 15 FREQUENCY (Hz) 20 0 5 10 15 FREQUENCY (Hz) 20 10 ______________________________________________________________________________________ Stereo Audio DAC with DirectDrive Headphone Amplifier MAX9850 Typical Operating Characteristics (continued) (DVDD = AVDD = PVDD = 3.0V, AGND = DGND = PGND = 0V, C1 = 0.47F, C2 = 2.2F, CNREG = CPREG = CREF = 1F, fS = 48kHz, fMCLK = 12.288MHz, master integer mode, headphone volume set to +6dB, both channels driven in-phase, TA = +25C, unless otherwise noted. fIN = 984.375Hz, A-weighted THD+N.) GAIN FLATNESS vs. FREQUENCY MAX9850toc31 SNR vs. MCLK MAX9850toc32 WIDEBAND FFT 0 -20 DAC IN = 0dBFS DAC IN TO LINE OUT fIN = 1kHz MAX9850toc33 1.0 0.8 0.6 0.4 GAIN (dB) RLOAD = 32 DAC IN TO HP DAC IN = 0dBFS 100 fICLK = fMCLK / 1 95 90 SNR (dB) fICLK = fMCLK / 2 fICLK = fMCLK / 4 fICLK = fMCLK / 3 20 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 10 100 1k FREQUENCY (Hz) 10k 100k VOUT (dBFS) 85 80 75 70 65 60 5 -40 -60 -80 -100 -120 -140 10 100 1k FREQUENCY (Hz) 10k 100k SLAVE NONINTEGER MODE DAC IN = -60dBFS fLRCLK = 32kHz, 44.1kHz, 48kHz AVDD = 3.0V 10 15 20 25 MCLK (MHz) 30 35 40 WIDEBAND FFT MAX9850toc34 OUTPUT POWER vs. TEMPERATURE AVDD = 1.8V THD+N = 1% RLOAD = 16 30 RLOAD = 32 25 20 15 10 MAX9850toc35 20 0 -20 VOUT (dBFS) -40 -60 -80 -100 -120 -140 10 100 1k FREQUENCY (Hz) 10k DAC IN = -60dBFS DAC IN TO LINE OUT fIN = 1kHz 40 35 OUTPUT POWER (mW) 100k -40 -15 10 35 60 85 TEMPERATURE (C) AVDD AND PVDD SUPPLY CURRENT vs. AVDD AND PVDD SUPPLY VOLTAGE MAX9850toc36 DIGITAL SUPPLY CURRENT vs. DVDD 9 DIGITAL SUPPLY CURRENT (mA) 8 7 6 5 4 3 2 1 0 TA = +85C, +25C, -40C MAX9850toc37 10 AVDD + PVDD SUPPLY CURRENT (mA) 9 8 7 6 5 4 3 2 TA = -40C TA = +25C TA = +85C 10 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 AVDD AND PVDD (V) 1.0 1.5 2.0 2.5 DVDD (V) 3.0 3.5 4.0 ______________________________________________________________________________________ 11 Stereo Audio DAC with DirectDrive Headphone Amplifier MAX9850 Pin Description PIN 1 NAME LRCLK FUNCTION Digital Audio Left-Right Clock Input/Output. LRCLK is the audio sample rate clock and determines whether the audio data on SDIN is routed to the left or right channel. LRCLK is an input when the MAX9850 is in slave mode and an output when in master mode. Digital Audio Bit Clock Input/Output. BCLK is an input when the MAX9850 is in slave mode and an output when in master mode. Digital Audio Serial Data Input Digital Power-Supply Input. Bypass to DGND with a 1F ceramic capacitor. Master Clock Input. All internal digital clocks are derived from MCLK. Digital Ground I2C Address-Select Input. Connect to AGND, AVDD, or SDA to select one of the three possible I2C addresses. General-Purpose Input/Output. Configure GPIO as an input or an output through the GPIO register. GPIO can perform the function of an interrupt when configured as an output. See the GPIO section. Right-Channel Line Input. INR is mixed with the right DAC output. Left-Channel Line Input. INL is mixed with the left DAC output. Line Level Right-Channel Output. OUTR is biased at AGND. Line Level Left-Channel Output. OUTL is biased at AGND. Reference Output. Bypass to AGND with a 1F ceramic capacitor. Analog Ground Line Output Negative Regulator Output. Bypass to AGND with a 1F capacitor. Line Output Positive Regulator Output. Bypass to AGND with a 1F capacitor. Analog Power Supply. Bypass to AGND with a 1F ceramic capacitor. Right-Channel Headphone Output. HPR is a DirectDrive output biased at AGND. Left-Channel Headphone Output. HPL is a DirectDrive output biased at AGND. Headphone Amplifier Negative Power-Supply Input. Connect to PVSS. Headphone Sense Input. Connect to the control pin of a headphone jack for automatic headphone sensing. Float HPS if unused. See the Headphone Sense Input section. Inverting Charge-Pump Output. Bypass to PGND with a 2.2F ceramic capacitor and connect to SVSS to provide the headphone amplifiers with a negative supply. Charge-Pump Flying Capacitor Negative Terminal. Connect a 0.47F ceramic capacitor between C1N and C1P. Charge-Pump Ground Charge-Pump Flying Capacitor Positive Terminal. Connect a 0.47F ceramic capacitor between C1P and C1N. Charge-Pump and Headphone Amplifier Positive Power-Supply Input. Bypass to PGND with a 1F ceramic capacitor. Connect to AVDD for normal operation. I2C-Compatible Serial Clock Input I2C-Compatible Serial Data Input/Output Exposed Thermal Pad. Connect EP to AGND. 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 -- BCLK SDIN DVDD MCLK DGND ADD GPIO INR INL OUTR OUTL REF AGND NREG PREG AVDD HPR HPL SVSS HPS PVSS C1N PGND C1P PVDD SCL SDA EP 12 ______________________________________________________________________________________ 1.8V TO 3.6V RIGHT LINE INPUT 1F 1F 1F 1F 0.1F 1F 1.8V TO 3.6V 5 MCLK DVDD AVDD CLOCK CONTROL AND DIGITAL PLL LINE OUT POSITIVE REGULATOR OUTR 11 LINE OUT REF PVDD AVDD INR PREG 4 13 26 17 16 9 MAX9850 3 SDIN 2 BCLK 1 LRCLK LINE OUT AMP SVSS INTERPOLATOR DIGITAL AUDIO INTERFACE RIGHT DAC VOLUME/MUTE CONTROL AVDD HPL 18 DSP DVDD HPS 21 10k 28 SDA LINE OUT AMP I2C INTERFACE LEFT DAC PVDD VOLUME/MUTE CONTROL 27 SCL 8 GPIO 7 ADD MONO 10k 10k AVDD HPR 19 C CHARGE PUMP SVSS C1P 25 23 22 20 24 6 14 10 0.1F LEFT LINE INPUT C1N PVSS SVSS PGND DGND AGND INL LINE OUT NEGATIVE REGULATOR NREG 15 1F SVSS OUTL 12 LINE OUT MAX9850 ______________________________________________________________________________________ C1 0.47F C2 2.2F Stereo Audio DAC with DirectDrive Headphone Amplifier Functional Diagram/Typical Operating Circuit 13 Stereo Audio DAC with DirectDrive Headphone Amplifier MAX9850 Detailed Description The MAX9850 audio digital-to-analog converter (DAC) with a stereo DirectDrive headphone amplifier is a complete digital audio playback solution. The sigma-delta DAC has 90dB of dynamic range and accepts stereo audio data at sampling frequencies ranging from 8kHz to 48kHz. Headphone output volume level, muting, and device configuration are programmed through the I2C-compatible interface. Three selectable I2C device IDs are available. Both basic modes of operation, integer and noninteger, provide full dynamic range performance and allow maximum flexibility when choosing the MAX9850's master clock (MCLK) frequency. Integer mode operation requires that MCLK is an integer multiple of 16 times the sample rate, and provides maximum full-scale SNR performance. Noninteger mode allows maximum flexibility when choosing an MCLK frequency, as the MCLK may be any frequency in the acceptable range. Audio data is sent to the MAX9850 through a 3-wire digital audio data bus that supports numerous input formats. LRCLK and BCLK signals are generated by the MAX9850 when configured in master mode. The MAX9850 can also be configured as a slave device, accepting LRCLK and BCLK signals from an external digital audio master. External LRCLK and BCLK signals may be either synchronous or asynchronous with MCLK when the MAX9850 is configured as a slave device. Maxim's DirectDrive architecture employs an internal charge pump to create a negative voltage supply to power the headphone amplifier outputs. The internal negative supply allows the analog output signals to be biased at ground, eliminating the need for an outputcoupling capacitor, reducing system cost and size. The MAX9850's stereo line inputs allow mixing of analog audio with digital audio. The summed audio signal is sent directly to the line and headphone outputs. The line inputs/outputs can be activated even when the DAC is disabled and MCLK is not present. The headphone sense input (HPS) detects when a headphone is connected to the MAX9850. The HPS circuit shuts down the headphone amplifier outputs when no headphones are connected. The headphone amplifiers can be automatically enabled when HPS detects the presence of headphones. samples. The resulting oversampled digital signal is then converted using a multibit sigma-delta modulator followed by an analog smoothing filter that greatly attenuates high-frequency quantization noise typical with oversampling converters. Flexible clocking modes allow the MAX9850 to be used effectively in applications normally not well suited for oversampling converters all without the need for expensive sample rate converters. Set DACEN = 0 in the enable register (register 0x5, bit B0) to disable the DAC. Set DACEN = 1 to enable the DAC. Line Outputs/Inputs The MAX9850 features line inputs (INR, INL) and line outputs (OUTR, OUTL). The line inputs allow a line level signal to be mixed with the DAC output, see the Functional Diagram/Typical Operating Circuit. Set LNIEN = 1 in the enable register (register 0x5, bit B1) to enable the line inputs. The line inputs are biased at AGND and can be directly coupled or AC-coupled to INR and INL, depending on the signal source. Stereo DirectDrive line outputs (OUTR and OUTL) can be used to drive line-level loads. Line outputs internally drive the inputs of the headphone amplifier. Set LNOEN = 1 in the enable register (register 0x5, bit B2) to enable the line outputs. Disabling the line outputs will also disable the headphone outputs. The internal charge pump must be enabled to operate the line outputs. Enable the charge pump by configuring CPEN(1:0) = 11 in the enable register (register 0x5, bit B5 and B4). See the Charge Pump section. DirectDrive Headphone and Line Amplifiers Unlike the MAX9850, traditional single-supply headphone amplifiers have their outputs biased about a nominal DC voltage, typically half the supply, for maximum dynamic range. Large coupling capacitors are typically needed to block this DC bias from the headphone. Without these capacitors, a significant amount of DC current flows to the headphone, resulting in unnecessary power dissipation and possible damage to both headphone and headphone amplifier. Maxim's patented DirectDrive architecture uses a charge pump to create an internal negative supply voltage. This allows the MAX9850 headphone and line outputs to be biased about ground, almost doubling the dynamic range while operating from a single supply. With no DC component, there is no need for the large DC-blocking capacitors. Instead of two large (33F to 330F) capacitors, the MAX9850 charge pump Sigma-Delta DAC The MAX9850 uses a sigma-delta DAC to achieve up to 91dB of SNR. The DAC receives a stereo digital input signal sampled at fLRCLK, interpolates the signal data to an 8 times fLRCLK frequency, and digitally filters the 14 ______________________________________________________________________________________ Stereo Audio DAC with DirectDrive Headphone Amplifier MAX9850 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 8 16 24 32 40 48 56 64 VOL(5:0) CODE Table 1. Slew-Rate Settings TYPICAL VOLUME SLEW RATE SR1 SR0 FROM FULL VOLUME TO MUTE 63s 125ms 63ms 42ms FROM FULL VOLUME TO VMN = 1 (ms) 0.1 200 100 67 HEADPHONE ATTENUATION (dB) 0 0 1 1 0 1 0 1 Figure 1. Headphone Amplifier Attenuation Profile requires only two small ceramic capacitors (0.47F and 2.2F), conserving board space, reducing cost, improving the frequency response, and THD of the headphone amplifier. In addition to the cost and size disadvantages, the DC-blocking capacitors required by conventional headphone amplifiers limit low-frequency response and decrease PSRR performance. Some dielectrics can significantly distort the audio signal. Volume Control Program VOL(5:0) in the volume register (register 0x2, bits B5-B0) to set the volume attenuation of the headphone amplifiers. Program VOL(5:0) to 0x00 for full volume. Minimum volume occurs at VOL(5:0) greater than or equal to 0x28. VMN in the status A register (register 0x0, bit B3) sets to 1 when the MAX9850 output is programmed to and reaches volume step 0x3F. Figure 1 shows the attenuation profile for each VOL(5:0) value. Volume Slew, Zero-Crossing Detect, and Mute Set SLEW = 1 in the volume register (register 0x2, bit B6) to enable the volume slew circuit. When SLEW = 1 headphone amplifier volume changes will slew between programmed levels smoothly. Set the volume slew rate with SR(1:0) in the charge-pump register (register 0x7, bits B7 and B6). Table 1 lists the volume slew-rate settings for each value of SR(1:0). Set ZDEN = 1 in the general-purpose register (register 0x3, bit B0) to force volume changes and headphone amplifier muting to occur when the audio signal is at its zero crossing. For optimal performance, set SR(1:0) to 01. This zero-crossing detection reduces audible clicks/pops caused when transitioning or slewing between volume levels. Set MUTE = 1 in the volume register (register 0x2, bit B7) to mute the headphone amplifiers. The mute function is independent of the volume control. The programmed volume settings are not reset when mute is enabled. With the zero-crossing detection and volume slew enabled, the Mute command mutes the output after the first zero crossing or after a 200ms timeout (SR = 01). Mono Mode Set MONO = 1 in the general-purpose register (register 0x3, bit B2) to enable mono mode. In mono mode, HPR is disabled, the left and right audio channels are summed and output on HPL. The 6dB attenuation ensures that the summed signal amplitude does not overdrive headphone amplifiers. SMONO in the status B register (register 0x1, bit B4) sets to 1 when the MAX9850 is in mono mode. Configuring the Headphone and Line Outputs Set HPEN and LNOEN in the enable register (register 0x5, bits B3 and B2) equal to 1 to enable the headphone outputs (HPR and HPL). Set HPEN or LNOEN = 0 to disable the headphone outputs. The headphone amplifier inputs are driven from the outputs of the line amplifier. Disabling the line out by setting LNOEN = 0 in the enable register (register 0x5, bit B2), deprives the headphone amplifiers of an input signal and disables the headphone outputs (HPR and HPL). The internal charge pump must be enabled to operate the headphone and line outputs. Enable the charge pump by programming CPEN(1:0) = 11 in the enable register (register 0x5, bits B5 and B4). See the Charge Pump section for more details. Headphone Sense Input (HPS) The headphone sense input (HPS) monitors the headphone jack, and automatically disables the headphone amplifiers based upon the voltage applied at HPS. For automatic headphone detection, connect HPS to the ______________________________________________________________________________________ 15 Stereo Audio DAC with DirectDrive Headphone Amplifier MAX9850 Table 2. HPS Debounce Times DVDD DBDEL(0) DBDEL(0) SHDN* DEBOUNCE TIME (ms) 0 2 17 DEBOUNCE TIME BASED ON fCP = 667kHz (ms) 0 (Disabled) Approx 200 Approx 400 Approx 800 0 0 100k 0 1 0 1 x 1 / fCP 1 1 218 x 1 / fCP 219 x 1 / fCP MAX9850 HPS GPIO Configure GPIO as an input or an output with the GPD bit in the general-purpose register (register 0x3, bit B5). GPD = 1 configures GPIO as an open-drain output while GPD = 0 makes GPIO an input. Connect an external pullup resistor from GPIO to DVDD when GPIO is configured as an output. GPIO as an output allows the MAX9850 to drive an LED or other state indicator. It also can be used to provide an interrupt signal to alert a C when an event has occurred. Potential events include changes in internal PLL lock state, connecting headphones to HPS, headphone outputs reaching the minimum volume, or an overcurrent on the headphone outputs. Any of these events can be programmed to pulse GPIO's output state when GPIO is configured as an open-drain output. Using GPIO as an input allows the MAX9850 to receive a signal from a C's digital I/O or other device. The status of GPIO is read through SGPIO in the status A register (register 0x0, bit B6). GPIO as an Output Set GPD = 1 (register 0x3, bit B5) to configure GPIO as an output. Program the output operating mode of GPIO with GM(1:0) in the general-purpose register (register 0x3, bits B7 and B6). GPIO can be programmed to output logic-high, a logic-low, or it can be programmed to output an interrupt signal by changing state when the ALERT bit in the status A register (register 0x0, bit B7) sets. Table 3 lists GPIO's modes of operation. *SHDN = 1 FOR THIS DIAGRAM Figure 2. Headphone Sense (HPS) Input control pin of a 3-wire headphone jack as shown in Figure 2. With no headphone present, the output impedance of the headphone amplifier pulls HPS to less than 0.3 x DVDD. When a headphone is inserted into the jack, the control pin is disconnected from the tip contact and HPS is pulled to DVDD through the internal 100k pullup. No external resistor is required. Leave HPS floating if automatic headphone sensing is not used. HPS must be high and HPEN (register 0x5, bit B3) must be set to 1 for the headphone amplifiers (HPR and HPL) to output an audio signal. The MAX9850 includes an HPS debounce circuit that ignores short duration changes on HPS. The debounce circuit ensures that a headphone is properly connected before powering up and enabling the headphone amplifiers. Program DBDEL(1:0) in the general-purpose register (register 0x3, bits B4 and B3) to set the HPS debounce delay time. The delay time is based on a division of the charge-pump frequency, fCP. See the Charge Pump section for details on programming the charge-pump frequency. Table 2 lists the available delay times of the debounce circuit. There is no delay on removal of a headphone when using automatic headphone sense. The headphone amplifiers are immediately placed into shutdown when HPS goes high. SHPS in the status A register (register 0x0, bit B4) reports the status of HPS. SHPS = 0 when HPS is low and SHPS = 1 when HPS is high. Table 3. GPIO Output Operating Modes (GPD = 1) GM(1) GM(0) 0 0 1 1 0 1 0 1 GPIO = 0 GPIO = High impedance GPIO = 0, ALERT output pulse enabled GPIO = High impedance, ALERT output pulse enabled MODE DESCRIPTION 16 ______________________________________________________________________________________ Stereo Audio DAC with DirectDrive Headphone Amplifier MAX9850 Table 4. Interrupt Enable Register (0x4) Events EVENT LCK (register 0x0, bit B5) sets when the internal PLL acquires or loses frequency lock SHPS (register 0x0, bit B4) sets after the headphone is inserted and the debounce time has elapsed when the headphone amplifier is powered up and ready VMN (register 0x0, bit B3) sets when the headphone amplifier minimum volume is reached IOHL or IOHR (register 0x0, bits B1 or B0) sets after an overcurrent at either HPL or HPR BIT NUMBER IN REGISTER 0x4 B5 B4 B3 B0 The interrupt enable register programs the MAX9850 to set ALERT = 1 when an event occurs. GPIO pulses when ALERT sets if GM(1:0) is programmed with 10 or 11. Table 4 contains a list of events that can set ALERT and their corresponding bit positions in the interrupt enable register. Enable the interrupt for each event by setting its bit to 1. GPIO as an Input The state of the GPIO input is read through SGPIO in the status A register (register 0x0, bit B6). Set ISGPIO = 1 to allow ALERT to set when SGPIO changes state. Higher ICLK frequencies provide higher SNR. Always use the highest acceptable ICLK. Sample rates other than those listed in Table 5 can be used. The MAX9850 defaults to IC(1:0) = 0x0 at power-up. DAC Operating Modes Four DAC operating modes: master integer, slave integer, master noninteger, and slave noninteger allow flexibility for operating with various applications and virtually any available MCLK frequency within the system. The operating modes are set with MAS in the digital audio register (register 0xA, bit B7) and INT in the LRCLK MSB register (register 0x8, bit B7). Table 6 shows the four modes of operation and the equations needed to program the MAX9850 to use the DAC modes. The master and slave integer modes are the modes in which DACs commonly operate. In these modes, LRCLK is ICLK divided by an integer value. A typical application would set MCLK equal to 256 x LRCLK. The MAX9850 requires that ICLK be an integer multiple of 16 x LRCLK where the integer multiple is at least 10 when in master or slave integer modes. Integer mode always provides the maximum full-scale signal level performance compared to other modes of operation. Choose integer mode over any other mode of operation when possible. The master noninteger mode allows for a condition where LRCLK and ICLK may not be related by an integer value. In these modes, the MAX9850 can operate from any available MCLK in the system. Internal Timing The internal clock (ICLK) and sample rate clock (LRCLK in master mode) are derived from MCLK. The MAX9850's flexible operating modes allow any desired LRCLK sample rate to operate over a wide range of MCLK input frequencies. Figure 3 shows a flowchart detailing how the internal clocks are derived from MCLK. The MAX9850 generates ICLK by dividing the MCLK frequency. Higher ICLK frequencies allow for greater DAC oversampling and SNR performance. Dynamic range of 90dB (typ) is possible when fICLK is greater than or equal to 12MHz. Lower ICLK frequencies may require slightly less supply current but sacrifice dynamic range. See the SNR vs. MCLK Frequency graph in the Typical Operating Characteristics. ICLK is a frequency-scaled version of MCLK that is used by the MAX9850 to clock the internal DAC circuitry and generate LRCLK and BCLK when in master mode. The charge-pump clock is derived from ICLK when the internal charge-pump oscillator is not used. Connect an available system clock to MCLK, see the Operating Modes section. MCLK can be supplied from any synchronous or available asynchronous system clock whose frequency falls within the 8.448MHz to 13MHz, or 16.896MHz to 40MHz range. Any MCLK within these ranges allow the MAX9850 to operate at any sample rate between 8kHz to 48kHz in either a master or slave mode of operation. Other MCLK frequencies can still be used, but will limit the sample rate ranges that the MAX9850 operates with as illustrated in Table 5. MASTER CLOCK (MCLK) IC(1:0) 0x0 = 1/1 0x1 = 1/2 0x2 = 1/3 0x3 = 1/4 INTERNAL CLOCK (ICLK) CP(4:0) LRCLK DIVIDER CHARGE-PUMP CLOCK LRCLK* *LRCLK IS GENERATED WHEN IN MASTER MODE ONLY. THE DIVIDER IS SET WITH THE LRCLK MSB AND LRCLK LSB REGISTERS. Figure 3. Internally Generated Clock Signals Derived from MCLK ______________________________________________________________________________________ 17 Stereo Audio DAC with DirectDrive Headphone Amplifier MAX9850 Table 5. Acceptable MCLK Frequency Ranges MINIMUM ICLK (MHz) LRCLK (kHz) INTEGER MODE (160 x fLRCLK) 1.280 1.764 1.920 2.560 3.528 3.840 5.120 7.056 7.680 NONINTEGER MODE (176 x fLRCLK) 1.4080 1.9404 2.1120 2.8160 3.8808 4.2240 5.6320 7.7616 8.4480 MAXIMUM ICLK (MHz) ANY MODE ACCEPTABLE MCLK FREQUENCIES* (MHz) IC(1:0) = 0x0 SF = 1 IC(1:0) = 0x1 SF = 2 IC(1:0) = 0x2 SF = 3 3.840 and 4.2240 to 39.0 5.292 and 5.8212 to 39.0 5.760 and 6.3360 to 39.0 7.680 and 8.4480 to 39.0 IC(1:0) = 0x3 SF = 4 5.120 and 5.6320 to 40.0 7.056 and 7.7616 to 40.0 7.680 and 8.4480 to 40.0 10.240 and 11.2640 to 40.0 8 11.025 12 16 22.05 24 32 44.1 48 13.0 13.0 13.0 13.0 13.0 13.0 13.0 13.0 13.0 1.280 and 2.560 and 1.4080 to 13.0 2.8160 to 26.0 1.764 and 3.528 and 1.9404 to 13.0 3.8808 to 26.0 1.920 and 3.840 and 2.1120 to 13.0 4.2240 to 26.0 2.560 and 5.120 and 2.8160 to 13.0 5.6320 to 26.0 3.528 and 7.056 and 10.584 and 14.112 and 3.8808 to 13.0 7.7616 to 26.0 11.6424 to 39.0 15.5232 to 40.0 3.840 and 7.680 and 11.520 and 15.360 and 4.2240 to 13.0 8.4480 to 26.0 12.6720 to 39.0 16.8960 to 40.0 5.120 and 10.240 and 15.360 and 20.480 and 5.6320 to 13.0 11.2640 to 26.0 16.8960 to 39.0 22.5280 to 40.0 7.056 and 14.112 and 21.168 and 28.224 and 7.7616 to 13.0 15.5232 to 26.0 23.2848 to 39.0 31.0464 to 40.0 7.680 and 15.360 and 23.040 and 30.720 and 8.4480 to 13.0 16.8960 to 26.0 25.3440 to 39.0 33.7920 to 40.0 *The first frequency listed is the minimum MCLK frequency required to operate in integer mode. The range of frequencies indicates the MCLK frequencies the MAX9850 needs to operate in any mode. Table 6. DAC Operating Modes SLAVE MODE (MAS = 0) MODE LRCLK and BCLK signals supplied from external source Asynchronous NONINTEGER MODE (INT = 0) LRCLK may be any frequency within an acceptable range MASTER MODE (MAS = 1) LRCLK and BCLK signals supplied by MAX9850 Asynchronous NMSB ,LSB = 0 NMSB ,LSB = Synchronous 222 x fLRCLK fICLK INTEGER MODE (INT = 1) ICLK and LRCLK must be synchronous and exact integer ratio related fICLK NLSB = , NMSB = 0 16 x fLRCLK 18 ______________________________________________________________________________________ Stereo Audio DAC with DirectDrive Headphone Amplifier Slave modes of operation allow the MAX9850 to operate in any audio system where the LRCLK and BCLK must be supplied from an external source. When operating in slave mode, the MCLK supplied to the MAX9850 may be either synchronous or asynchronous with LRCLK. Use the slave integer mode if ICLK is synchronous and has an integer multiple of 16 x LRCLK. Integer mode ensures that the highest levels of full-scale-input signal performance can be achieved. Slave noninteger mode offers the highest degree of clock flexibility. ICLK does not need to be synchronous or an integer multiple of LRCLK when operating in slave noninteger mode. Master modes of operation allow the MAX9850 to generate and supply an LRCLK and BCLK to other elements in the system. Use master integer mode if the provided ICLK is an integer multiple of 16 x LRCLK. Integer mode ensures that the highest levels of full-scale input signal performance can be achieved. Master noninteger mode allows the MAX9850 to supply virtually any frequency LRCLK with an accuracy better than 0.5%. The slave noninteger mode provides maximum flexibility for ICLK and LRCLK frequencies. The ICLK and LRCLK can be asynchronous and noninteger related. Connect any available system clock that is listed on Table 5 in the Internal Timing section. In slave noninteger mode, the acceptable MCLK frequency range is the same as master mode. Master Integer Mode (MAS = 1, IM = 1) The MAX9850 generates the LRCLK and BCLK in master mode. LRCLK is an integer factor of ICLK by the following equation: fLRCLK = where: fICLK = ICLK frequency. fICLK must be at least 160 x fLRCLK for proper DAC operation. NLSB = decimal value of the data contained in LSB(7:0) (register 0x9, bits B7-B0). fLRCLK = LRCLK frequency. For example: fICLK = 12.228MHz and NLSB = 16 (0x10), fLRCLK = 48kHz. Solve the above equation for NLSB. Use master integer mode if N LSB is an integer. Use master noninteger mode if NLSB is not an integer. fICLK 16 x NLSB Slave Integer Mode (MAS = 0, IM = 1) The MAX9850 accepts LRCLK and BCLK from an external digital audio source when in slave integer mode. LRCLK must be an exact integer multiple of ICLK to ensure proper operation. Program LSB(7:0) (register 0x9, bits B7-B0) with the LRCLK division ratio. Use the following equation to find the value that needs to be programmed to LSB(7:0): NLSB = fICLK 16 x fLRCLK MAX9850 where: fICLK = ICLK frequency. fICLK must be 160 x fLRCLK for proper DAC operation. fLRCLK = supplied LRCLK frequency. NLSB = decimal value of the data contained in LSB(7:0) (register 0x9, bits B7-B0). For example: fICLK = 11.2896MHz and fLRCLK = 44.1kHz, NLSB = 16 (0x10). Solve the above equation for NLSB. Use slave integer mode if NLSB is an integer. Use slave noninteger mode if NLSB is not an integer. Slave Noninteger (MAS = 0, IM = 0) In slave noninteger mode, the MAX9850 accepts an external LRCLK and converts the digital audio signal using any asynchronous ICLK within the acceptable operating range. The MAX9850 uses internal clock recovery circuitry to generate all required internal clocks. This allows the MAX9850 to operate in systems that do not have dedicated clock sources or crystal oscillators. Virtually any existing system clock will work. fICLK must be at least 176 x fLRCLK for proper operation. Master Noninteger Mode (MAS = 1, IM = 0) The ICLK frequency in some applications may not be an integer multiple of the desired LRCLK frequency. The MAX9850, operating in master noninteger mode, can generate and output any LRCLK frequency between 8kHz to 48kHz (0.5%) with any ICLK frequency within the acceptable operating range. In this mode, the MAX9850 generates LRCLK by dividing MCLK by the ratio programmed into MSB(14:8) and LSB(7:0) (register 0x8, bits B7-B0 and register 0x9, bits B6-B0). The LRCLK sample frequency can have any noninteger relationship with respect to MCLK. Calculate the values for MSB(14:8) and LSB(7:0) with the following equation: 222 x f LRCLK NMSB ,LSB = ROUND fICLK 19 ______________________________________________________________________________________ Stereo Audio DAC with DirectDrive Headphone Amplifier MAX9850 where: fICLK = ICLK frequency. fICLK must be at least 176 x fLRCLK for proper DAC operation. fLRCLK = LRCLK frequency. NMSB,LSB = decimal value of MSB(14:8) and LSB(7:0) (register 0x8, bits B6-B0 and register 0x9, bits B7-B0). Round the results of the equation to the nearest integer value. For example: fLRCLK = 44.1kHz, fICLK = 12.288MHz. 1) Solve for NMSB,LSB, 15052.8. 2) Round result to nearest integer value. 15053. 3) Convert to hex, 0x3CD. 4) Program MSB(14:8) with the MSB 0x3A and program LSB(7:0) with the LSB 0xCD). Table 7 provides examples of using master noninteger mode with various MCLK frequencies to generate useful LRCLK frequencies. The state of CP(4:0), in the charge-pump register (register 0x7, bits B4-B0), determines whether the charge-pump oscillator is derived from the internal 667kHz oscillator or from MCLK. Set CPEN(1:0) = 11 and set CP(4:0) = 0x00 to enable the internal oscillator. The charge pump runs independent from MCLK when the internal oscillator is enabled allowing the charge pump to operate when the DAC is disabled or when only the line inputs are used. No MCLK is required when only the line inputs are used. The switching frequency of the charge pump is well beyond the audio range and does not interfere with audio signals. The switch drivers utilize techniques that minimize noise generated by turn-on and turn-off transients. Although not typically required, additional high-frequency noise attenuation can be achieved by increasing the size of C2 and the PVDD bypass capacitor (see the Functional Diagram/Typical Operating Circuit). Derive the charge-pump clock from MCLK by programming CP(4:0) to a non-zero value based on the following equation: fMCLK NCP(4:0) = 2 x fCP x SF where: fMCLK = MCLK frequency. f CP = charge-pump clock frequency. Ensure fCP = 667kHz 20% for proper operation. SF = MCLK scale factor. SF is the decimal value of IC(1:0) + 1. NCP(4:0) = rounded decimal value of CP(4:0) (register 0x7, bits B4-B0). NCP(4:0) must be greater than 1 when deriving the charge-pump clock from ICLK. Charge Pump The DirectDrive line and headphone outputs of the MAX9850 require a charge pump to create the internal negative power supply. Set CPEN(1:0) = 11 in the enable register (register 0x5, bits B5 and B4) to turn on the charge pump. The negative charge-pump voltage is established and the audio outputs are ready for use approximately 1.4ms after CPEN is set to 11. Table 7. Master Noninteger NMSB,LSB Examples N (15-BIT hex VALUE) MCLK (MHz) 18.4320 16.9344 16.3840 12.5000 12.2880 12.0000 11.2896 9.2160 8.4672 8.4480 SF 2 2 2 1 1 1 1 1 1 1 ICLK (MHz) 48 9.2160 8.4672 8.1920 12.5000 12.2880 12.0000 11.2896 9.2160 8.4672 8.4480 3EEA 4000 4189 45A9 5555 5CE1 5D17 5555 5CE1 44.1 4E66 5555 5833 39CE 3ACD 3C36 4000 4E66 5555 5587 32 38E4 3DEB 4000 29F1 2AAB 2BB1 2E71 38E4 3DEB 3E10 LRCLK OUTPUT FREQUENCY (kHz) 24 2AAB 2E71 3000 1F75 2000 20C5 22D4 2AAB 2E71 2E8C 22.05 2733 2AAB 2C1A 1CE7 1D66 1E1B 2000 2733 2AAB 2AC3 16 1C72 1EF6 2000 14F9 1555 15D8 1738 1C72 1EF6 1F08 12 1555 1738 1800 0FBB 1000 1062 116A 1555 1738 1746 11.03 139A 1555 160D 0E73 0EB3 0F0E 1000 139A 1555 1562 8 0E39 0F7B 1000 0A7C 0AAB 0AEC 0B9C 0E39 0F7B 0F84 Note: The N values represent the combined MSB(14:8) and LSB(7:0) values. 20 ______________________________________________________________________________________ Stereo Audio DAC with DirectDrive Headphone Amplifier For example: f MCLK = 12MHz, SF = 1, and f CP = 666.7kHz, NCP(4:0) = 9. Table 8 shows recommended CP(4:0) values for typical MCLK frequencies. MAX9850 Table 8. Recommended CP(4:0) Values for Typical MCLK Frequencies fMCLK (MHz) 11.2896 12.0000 12.2880 13.0000 24.0000 27.0000 CP(4:0) 0x08 0x09 0x09 0x0A 0x09 0x07 IC(1:0) 0x0 0x0 0x0 0x0 0x1 0x2 SF 1 1 1 1 2 3 fCP (kHz) 705.6 666.7 682.7 650.0 666.7 642.9 Registers and Bit Descriptions Eleven internal registers program and report the status of the MAX9850. Table 9 lists all of the registers, their addresses, and power-on-reset state. Registers 0x0 and 0x1 are read-only while all of the other registers are read/write. Register 0xB is reserved for factory testing. Status Registers (0x0, 0x1) Table 9. Register Map REGISTER Status A Status B Volume General Purpose Interrupt Enable Enable Clock Charge Pump LRCLK MSB LRCLK LSB Digital Audio MAS INV BCINV 0 SHDN 0 SR(1:0) INT B7 ALERT X MUTE B6 SGPIO X SLEW GPD ILCK B5 LCK X B4 SHPS SMONO B3 VMN SHP VOL(5:0) DBDEL(1:0) ISHPS IVMN HPEN MONO 0 LNOEN 0 0 LNIEN 0 ZDEN IIOH DACEN 0 B2 1 SLO B1 IOHL SLI B0 IOHR SDAC REGISTER ADDRESS 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 RTJ WS(1:0) 0xA 0xB POWER-ON RESET STATE -- -- 0x0C 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 -- GM(1:0) ISGPIO MCLKEN 0 CPEN(1:0) 0 0 0 IC(1:0) CP(4:0) MSB(14:8) LSB(7:0) LSF DLY RESERVED X = Don't Care. ______________________________________________________________________________________ 21 Stereo Audio DAC with DirectDrive Headphone Amplifier MAX9850 Alert Flag (ALERT) Table 10. Status A (0x0) Read-Only, Bit Descriptions B7 B6 B5 LCK B4 SHPS B3 VMN B2 1 B1 IOHL B0 IOHR ALERT SGPIO PLL Lock Status (LCK) 1 = The internal PLL is locked with LRCLK. 0 = The internal PLL is not locked with LRCLK. LCK reports the lock status of the internal PLL at the time that STATUS A is read. The DAC is disabled when the PLL is not locked. When the PLL is locked with LRCLK, the DAC will become operational if DACEN is equal to 1 (register 0x5, bit B0). ALERT sets to 1 when LCK changes state if ILCK = 1 in the interrupt enable register (register 0x4, bit B5). HPS Status (SHPS) 1 = HPS is low, indicating that headphones are connected. 0 = HPS is high, indicating no headphone is connected. SHPS reports the debounced status of HPS at the time STATUS A is read. SHPS = 0 indicates that no headphone is connected and HPS is high. SHPS sets to 1 when HPS is low, indicating headphones are connected. ALERT sets to 1 when SHPS changes state, if ISHPS = 1 in the interrupt enable register (register 0x4, bit B4). Volume at Minimum (VMN) 1 = Headphone volume has reached its minimum volume. 0 = Headphone volume is not at its minimum. VMN sets to 1 when the minimum headphone amplifier volume has been reached. ALERT sets to 1 when IVMN = 1 in the interrupt enable register (register 0x4, bit B3). Headphone Overcurrent Left (IOHL) 1 = The left headphone output (HPL) has experienced an overcurrent condition. 0 = The left headphone output (HPL) is operating normally. IOHL sets to 1, when an overcurrent occurs on the left headphone output HPL and remains set until status A is read. ALERT sets to 1 when an overcurrent on the right or left headphone output occurs if IIOH = 1 in the interrupt enable register (register 0x4, bit B0). Headphone Overcurrent Right (IOHR) 1 = The right headphone output (HPR) has experienced an overcurrent condition. 0 = The right headphone output (HPR) is operating normally. IOHR sets to 1 and remains set until STATUS A is read. ALERT sets to 1 when an overcurrent on the right or left headphone output occurs if IIOH = 1 in the interrupt enable register (register 0x4, bit B0). 1 = An interrupt event has occurred. 0 = No interrupt event has occurred. ALERT is an alert flag that sets when an interrupt event has occurred. The events that can be programmed to set ALERT are as follows: * A change in state on SGPIO indicating a change in levels at GPIO when GPIO is configured as an input. Configure GPIO as an input and set ISGPIO = 1 in the interrupt enable register (register 0x4, bit B6). * The internal PLL locks or unlocks with LRCLK. Set ILCK = 1 in the interrupt enable register (register 0x4, bit B5). * A change in state on SHPS indicating headphones have been connected or disconnected. Set ISHPS = 1 in the interrupt enable register (register 0x4, bit B4). * The headphone amplifier reaches its minimum volume. Set IVMN = 1 in the interrupt enable register (register 0x4, bit B3). An overload on either right or left headphone outputs (HPR, HPL). Set IIOH = 1 in the interrupt enable register (register 0x4, bit B0). * ALERT sets to 1 after an event occurs and remains set until the status A register is read. GPIO configured as an output can interrupt a C on an ALERT event. GM(1:0) in the GPIO register (register 0x3, bits B7 and B6) control the output mode of GPIO. See the GPIO section for more information on programming GPIO as an output. GPIO Status (SGPIO) 1 = GPIO is high. 0 = GPIO is low. SGPIO reports the status of GPIO at the time that status A is read, regardless of whether GPIO is programmed as an input or output. A change in state on SGPIO causes ALERT to set to 1 when GPIO is configured as an input and ISGPIO = 1 in the interrupt enable register (register 0x4, bit B6). 22 ______________________________________________________________________________________ Stereo Audio DAC with DirectDrive Headphone Amplifier Table 11. Status B (0x1) Read-Only, Bit Descriptions B7 X B6 X B5 X B4 SMONO B3 SHP B2 SLO B1 SLI B0 SDAC Line Output Status (SLO) 1 = The line outputs are enabled. 0 = The line outputs are disabled. SLO indicates whether the line outputs are enabled or disabled. Set LNOEN = 1 in the enable register (register 0x5, bit B2) to enable the line outputs. Line Input Status (SLI) 1 = The line inputs are enabled. 0 = The line inputs are disabled. SLI indicates whether the line inputs are enabled or disabled. Set LNIEN = 1 in the enable register (register 0x5, bit B1) to enable the line inputs. DAC Status (SDAC) 1 = The DAC is operating. 0 = The DAC is not operating. SDAC indicates whether the DAC is operational and receiving valid clock signals, or not operating. MAX9850 Mono Status (SMONO) 1 = The headphone amplifier outputs are in mono mode. 0 = The headphone amplifier outputs are in stereo mode. SMONO indicates whether the headphone outputs are in mono or stereo mode. In mono mode, the left and right audio signals are mixed and output to the left headphone output. Set MONO = 1 in the general-purpose register (register 0x3, bit B2) to enter mono mode. Headphone Amplifier Status (SHP) 1 = The headphone amplifiers are operating. 0 = The headphone amplifiers are not operating. SHP indicates whether the headphone amplifiers are operating or not operating. ______________________________________________________________________________________ 23 Stereo Audio DAC with DirectDrive Headphone Amplifier MAX9850 Volume Register (0x2) Table 12. Volume (0x2) Read/Write, Bit Descriptions B7 B6 B5 B4 B3 B2 B1 B0 MUTE SLEW VOL(5:0) Slew-Rate Control Enable (SLEW) 1 = Enable slew-rate control. 0 = Disable slew-rate control. The slew-rate control allows the headphone amplifiers to smoothly slew between volume settings after a volume change is made. Volume changes occur immediately when the slew-rate control is disabled. Volume Control (VOL(5:0)) VOL(5:0) controls the headphone amplifier volume attenuation. Code 0x00 is full volume while 0x28 to 0x3F is full attenuation. VMN sets to 1 when code 0x3F is programmed and the minimum volume is reached. Table 13 lists the volume attenuation settings for each code. Mute Enable (MUTE) 1 = Mute headphone outputs. 0 = Unmute headphone outputs. Set MUTE = 1 to mute the headphone outputs (HPR, HPL). The headphone output is muted on the first zero crossing of the audio signal if zero-crossing detect is enabled. Table 13. Volume Control Settings VOL(5:0) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D SETTING (dB) +6.0 +5.5 +5.0 +4.5 +4.0 +3.5 +3.0 +2.5 +1.5 +0.5 -0.5 -1.5 -3.5 -5.5 VOL(5:0) 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B SETTING (dB) -7.5 -9.5 -11.5 -13.5 -15.5 -17.5 -19.5 -21.5 -23.5 -25.5 -27.5 -29.5 -31.5 -33.5 VOL(5:0) 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28-0x3F -- SETTING (dB) -35.5 -37.5 -39.5 -41.5 -45.5 -49.5 -53.5 -57.5 -61.5 -65.5 -69.5 -73.5 Mute -- 24 ______________________________________________________________________________________ Stereo Audio DAC with DirectDrive Headphone Amplifier General-Purpose Register Table 14. General Purpose (0x3) Read/Write, Bit Descriptions B7 B6 B5 GPD B4 B3 B2 MONO B1 0 B0 ZDEN GM(1:0) DBDEL(1:0) Volume changes, headphone output muting, and entering/exiting shutdown occur only on the zero crossing of the audio signal when ZDEN = 1. For optimum performance, set SR(1:0) to 01. MAX9850 Interrupt Enable Register GPIO Output Mode Control (GM(1:0)) 00 = GPIO outputs low. 01 = GPIO is high impedance. 10 = GPIO outputs low and the ALERT output pulse function is enabled. 11 = GPIO is high impedance and the ALERT output pulse function is enabled. GM(1:0) programs the GPIO output state and enables or disables the ALERT output pulse function. The opendrain GPIO output can be programmed to output static high or a low. GPIO can also be programmed to pulse to the opposite output level than the programmed output state when an alert occurs. An alert occurs when ALERT sets to 1 in the status A register. GM(1:0) has no function when GPIO is configured as an input. GPIO Direction (GPD) 1 = Configure GPIO as an open-drain output. 0 = Configure GPIO as an input. The state of GPD determines whether GPIO is an input or an output. Debounce Delay Control (DBDEL(1:0)) 00 = HPS debounce delay disabled. 01 = HPS debounce delay is a nominal 200ms. 10 = HPS debounce delay is a nominal 400ms. 11 = HPS debounce delay is a nominal 800ms. DBDEL(1:0) controls the length of HPS debounce time. The debounce time is derived from the charge-pump clock. Mono Mode Enable (MONO) 1 = Enable mono mode. 0 = Disable mono mode, headphone outputs in stereo mode. Set MONO = 1 to force the headphone outputs to mono mode. The stereo input signal is summed to one channel. The summed signal is output on the left headphone output (HPL). Zero-Detect Enable (ZDEN) 1 = Enables the zero-detect function. 0 = Disables the zero-detect function. Table 15. Interrupt Enable (0x4) Read/Write, Bit Descriptions B7 0 B6 ISGPIO B5 ILCK B4 B3 B2 0 B1 0 B0 IIOH ISHPS IVMN Note: Any of the below interrupts can be configured to trigger a hardware interrupt through GPIO. Program GPD and GM(1:0) in the general-purpose register to enable the ALERT output pulse function. SGPIO Interrupt Enable (ISGPIO) 1 = A state change on SGPIO, when GPIO is an input, will cause ALERT to set to 1. 0 = A state change on SGPIO, when GPIO is an input, will not cause ALERT to set. ISGPIO = 1 configures the MAX9850 to set ALERT = 1 when SGPIO changes state. The interrupt may only be enabled when GPIO is an input. PLL Lock Interrupt Enable (ILCK) 1 = A state change on LCK will cause ALERT to set to 1. 0 = A state change on LCK will not cause ALERT to set. ILCK = 1 configures the MAX9850 to set ALERT = 1 when the DAC's internal PLL loses or achieves frequency lock with LRCLK. Program GM(1:0), while GPD = 1, to configure GPIO as a hardware interrupt to alert a C when LCK changes state. SHPS Interrupt Enable (ISHPS) 1 = A state change on SHPS will cause ALERT to set to 1. 0 = A state change on SHPS will not cause ALERT to set. ISHPS = 1 configures the MAX9850 to set ALERT = 1 when SHPS changes state. Volume at Minimum Interrupt Enable (IVMN) 1 = A state change on VMN will cause ALERT to set to 1. 0 = A state change on VMN will not cause ALERT to set. IVMN = 1 configures the MAX9850 to set ALERT = 1 when the headphone amplifier is programmed to and reaches its minimum output volume. Program GM(1:0), while GPD = 1, to configure GPIO as a hardware interrupt to alert a C when the headphone output volume is programmed to and reaches its minimum volume. ______________________________________________________________________________________ 25 Stereo Audio DAC with DirectDrive Headphone Amplifier MAX9850 Headphone Overcurrent Interrupt Enable (IIOH) 1 = ALERT sets to 1 when either IOHL or IOHR set to 1. 0 = ALERT will not set when IOHL or IOHR set to 1. IIOH = 1 configures the MAX9850 to set ALERT = 1 when one or both of the headphone amplifier outputs (HPL, HPR) has experienced an overcurrent condition. Program GM(1:0), while GPD = 1, to configure GPIO as a hardware interrupt to alert a C to an overcurrent condition on the headphone outputs. Line Output Enable (LNOEN) 1 = Enable the line outputs. 0 = Disable the line outputs. LNOEN = 0 forces the line outputs and the headphone outputs to high impedance. Set LNOEN = 1 to enable the line outputs. The line outputs must be enabled for the headphone amplifiers to operate properly. Line Input Enable (LNIEN) 1 = Enable the line outputs. 0 = Disable the line outputs. LNIEN = 1 enables the line inputs. LNIEN = 0 disconnects the line inputs. DAC Enable (DACEN) 1 = Enable the audio DAC. 0 = Disable the audio DAC. DACEN = 1 enables the DAC and all supporting circuitry including the digital audio interface and interpolating FIR filter. DACEN = 0 places the DAC and support circuitry into low-power shutdown mode. Enable Register Table 16. Enable (0x5) Read/Write, Bit Descriptions B7 B6 B5 B4 B3 B2 B1 B0 SHDN MCLKEN CPEN (1:0) HPEN LNOEN LNIEN DACEN Shutdown (SHDN) 1 = The MAX9850 is powered on. 0 = The MAX9850 is in low-power shutdown mode. The I2C interface remains active. Set SHDN = 1 to power on the MAX9850. The headphone amplifier, master clock, line inputs/outputs, DAC, charge pump, and charge-pump clock all have their own enable bits. The individual components of the MAX9850 can only be enabled after SHDN = 1. MCLK Enable (MCLKEN) 1 = MCLK is connected to the MAX9850. 0 = MCLK is disconnected from the MAX9850. MCLKEN must be set to 1 for the DAC to operate properly. The line inputs/outputs and headphone amplifiers will work if MCLKEN = 0, but the charge-pump clock must be derived from the internal oscillator. Charge-Pump Enable (CPEN(1:0)) 11 = Enable the internal charge pump. 00 = Disable the internal charge pump. 10 and 01 = Invalid. Set CPEN(1:0) to 11 to enable the internal charge pump when the line outputs and headphone amplifiers are used. Headphone Output Enable (HPEN) 1 = Enable the headphone outputs. 0 = Disable the headphone outputs. Set HPEN = 1 to enable the headphone outputs. HPEN = 0 places the headphone outputs in high impedance. The line outputs must be enabled for the headphone amplifiers to operate properly. 26 Clock Register Table 17. Clock (0x6) Read/Write, Bit Descriptions B7 0 B6 0 B5 0 B4 0 B3 B2 B1 0 B0 0 IC(1:0) Internal Clock Divide (IC(1:0)) 00 = Internal clock divider is transparent (f ICLK = fMCLK). 01 = (fICLK = fMCLK / 2). 10 = (fICLK = fMCLK / 3). 11 = (fICLK = fMCLK / 4). IC(1:0) controls the internal clock divider that determines the internal clock frequency from the master clock. Charge-Pump Register Table 18. Charge Pump (0x7) Read/Write, Bit Descriptions B7 B6 B5 0 B4 B3 B2 CP(4:0) B1 B0 SR(1:0) ______________________________________________________________________________________ Stereo Audio DAC with DirectDrive Headphone Amplifier Slew-Rate Control (SR(1:0)) 00 = Headphone volume slews from code 0x00 to 0x28 in 63s. Not recommended when ZDEN = 1. 01 = Headphone volume slews from code 0x00 to 0x28 in 125ms. 10 = Headphone volume slews from code 0x00 to 0x28 in 63ms. 11 = Headphone volume slews from code 0x00 to 0x28 in 42ms. Program SR(1:0) to set the rate that the MAX9850 uses to slew between two volume settings. The slew-rate control also controls the amount of time the headphone outputs take to mute or shut down after the command is given. Charge-Pump Clock Divider (CP(4:0)) CP(4:0) controls the charge-pump clock divider. The charge-pump clock frequency (fCPCLK) is derived from either ICLK or from the internal oscillator. Program CP(4:0) = 0x00 to enable the 667kHz internal oscillator. This allows the headphone amplifiers and line outputs to operate when the DAC is disabled. Programming CP(4:0) to any value other than 0x00 disables the internal oscillator and derives the chargepump clock from ICLK. Program CP(4:0) with a value that creates a 667kHz 20% charge-pump clock from ICLK by the following equation: fCP = fMCLK 2 x NCP(4:0) x SF Integer mode operation requires that ICLK is an integer multiple of 16 times the sample rate (fLRCLK). See the DAC Operating Modes section. When in integer mode, fLRCLK = fICLK / (16 x LSB(7:0)). LRCLK MSB Divider (MSB(14:8)) MSB(14:8) and LSB(7:0) are used to determine fLRCLK when in noninteger mode only (see the DAC Operating Modes section). For noninteger mode: NMSB ,LSB = 222 x fLRCLK fICLK MAX9850 LRCLK LSB Divider (LSB(7:0)) LSB(7:0) combined with MSB(14:8) sets the LRCLK divider when the MAX9850 is configured in noninteger mode. Only LSB(7:0) is used to determine fLRCLK when the MAX9850 is configured in integer mode. See the DAC Operating Modes section. Digital Audio Register Table 20. Digital Audio (0xA) Read/Write, Bit Descriptions B7 MAS B6 INV B5 BCINV B4 LSF B3 DLY B2 RTJ B1 B0 WS(1:0) where: fMCLK = MCLK frequency. NCP(4:0) = decimal value of CP(4:0). NCP(4:0) must be greater than 1 when deriving the charge-pump clock from ICLK. fCP = charge-pump clock frequency. Program fCP = 667kHz 20% for proper operation. SF = MCLK scale factor. SF is the decimal value of IC(1:0) + 1. Master Mode (MAS) 1 = Configure the MAX9850 to master mode. 0 = Configure the MAX9850 to slave mode. Set MAS = 1 to configure the MAX9850 to master mode. The LRCLK and BCLK are generated by the MAX9850 when in master mode. Set MAS = 0 to configure the MAX9850 as a digital audio slave that accepts LRCLK and BCLK from an external digital audio source. LRCLK Invert (INV) 1 = Left audio data is clocked in when LRCLK is high and right data is clocked in when LRCLK is low. 0 = Left audio data is clocked in when LRCLK is low and right data is clocked in when LRCLK is high. Set INV = 0 to conform to the I2S standard. Bit Clock Invert (BCINV) 1 = Digital data at SDIN latches in on the falling edge of BCLK. 0 = Digital data at SDIN latches in on the rising edge of BCLK. Set BCINV = 0 to conform to the I2S standard. LRCLK MSB and LRCLK LSB Registers Table 19. LRCLK MSB (0x8) and LRCLK LSB (0x9) Read/Write, Bit Descriptions B7 INT B6 B5 B4 B3 MSB(14:8) LSB(7:0) B2 B1 B0 Integer Mode (INT) 1 = Configure the MAX9850 to integer mode. 0 = Configure the MAX9850 to noninteger mode. ______________________________________________________________________________________ 27 Stereo Audio DAC with DirectDrive Headphone Amplifier MAX9850 Least Significant Bit First (LSF) 1 = Accepts audio data LSB first. 0 = Accepts audio data MSB first. Set LSF = 0 to conform to the I2S standard. SDIN Delay (DLY) 1 = Audio data is latched into the MAX9850 on the second rising BCLK edge after LRCLK transitions. 0 = Audio data is latched into the MAX9850 on the first rising BCLK edge after LRCLK transitions. Set DLY = 1 to conform to the I2S standard. Right-Justified Data (RTJ) 1 = Audio data is right justified. 0 = Audio data is left justified. I2S audio data is left justified. Set RTJ = 0 to conform to the I2S standard. Word Length Select (WS (1:0)) 00 = Audio data word length is 16 bits. 01 = Audio data word length is 18 bits. 10 = Audio data word length is 20 bits. 11 = Audio data word length is 24 bits. Program WS(1:0) to select the input data word length. Programming the audio data word length ensures that the correct number of BCLK cycles are output to accommodate the incoming data word. The MAX9850 generates the BCLK and the LRCLK from ICLK when in master mode, see the Internal Timing section. In slave mode, the MAX9850 accepts an LRCLK and BCLK from an external digital audio source. The MAX9850 can accept right- or left-justified data when operating in slave mode with extra BCLK pulses beyond what is programmed by the WS(1:0) bits. When using the I2S standard, audio data must latch into SDIN on the second BCLK rising edge following an LRCLK transition. See Figure 4 for the various relationships between clock and data that are supported by the MAX9850. The MAX9850 can be configured to accept 16, 18, 20, or 24-bit data. The MAX9850 generates exactly the programmed number of BCLK cycles when in master mode. Program the audio data word size with WS(1:0) (register 0xA, bit B0 and B1) according to Table 22 to ensure that the MAX9850 outputs the correct number of BCLK cycles to accommodate the input word. Table 22. Audio Data Word Size WS(1:0) 0x0 0x1 0x2 0x3 DATA WORD SIZE (BITS) 16 18 20 24 Digital Audio Interface The MAX9850 receives serial digital audio data through a 3-wire interface. The data can be right or left justified, MSB or LSB first, or I2S compatible. The 3-wire serial bus carries two time-multiplexed audio data channels (SDIN), a channel-select line (LRCLK), and a bit clock line (BCLK). The configuration of the audio interface is controlled with the digital audio register, see Table 20. Typical digital audio formats, and the required digital audio register code, are listed in Table 21. Figure 4. illustrates the difference between right justified, left justified, and I2S-compatible audio data. The internal digital processing resolution is 18 bits wide. Data words longer than 18 bits will be truncated. Zeros are internally programmed into the missing bit positions when the data word is shorter than the programmed word size. I2C-Compatible Serial Interface The MAX9850 features an I2C/SMBusTM-compatible, 2wire serial interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate communication between the MAX9850 and the master at clock rates up to 400kHz. Figure 5 shows the 2-wire interface timing diagram. The master generates SCL and initiates data transfer on the bus. A master device writes data to the MAX9850 by transmitting the proper slave address followed by the register address and then the data word. Each transmit sequence is framed by a START (S) or REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted to the MAX9850 is 8 bits long and is followed by an acknowledge clock pulse. Table 21. Typical Digital Audio Formats FORMAT Left-Justified Audio Data Right-Justified Audio Data I2S-Compatible Audio Data DIGITAL AUDIO REGISTER CODE (0xA) X0000000 X0000100 X0001000 SMBus is a trademark of Intel Corp. 28 ______________________________________________________________________________________ Stereo Audio DAC with DirectDrive Headphone Amplifier MAX9850 I2S DIGITAL AUDIO REGISTER (0xA) CONTENTS = 00001000 LRCLK SDIN BCLK LEFT-JUSTIFIED DIGITAL AUDIO REGISTER (0xA) CONTENTS = 00000000 LRCLK SDIN BCLK RIGHT-JUSTIFIED DIGITAL AUDIO REGISTER (0xA) CONTENTS = 00000100 LRCLK SDIN BCLK LEFT 15 14 13 12 11 10 9 876543210 RIGHT 15 14 13 12 11 10 9 876543210 15 14 13 12 11 10 9 LEFT 876543210 15 14 13 12 11 10 9 RIGHT 876543210 X 15 14 13 12 11 10 9 LEFT 876543210 X 15 14 13 12 11 10 9 RIGHT 876543210 Figure 4. Right-Justified, Left-Justified and I2S Audio Data Formats (Slave Mode, 16-Bit Data) SDA tSU, DAT tLOW SCL tHD, STA tR START CONDITION tHIGH tF REPEATED START CONDITION STOP CONDITION START CONDITION tHD, DAT tHD, STA tBUF tHD, STA tSP tSU, STO Figure 5. 2-Wire Interface Timing Diagram A master reading data from the MAX9850 transmits the proper slave address followed by a series of nine SCL pulses. The MAX9850 transmits data on SDA in sync with the master-generated SCL pulses. The master acknowledges receipt of each byte of data. Each read sequence is framed by a START (S) or REPEATED START (Sr) condition, a not acknowledge, and a STOP (P) condition. SDA operates as both an input and an open-drain output. A pullup resistor, typically greater than 500, is required on the SDA bus. SCL operates as an input only. A pullup resistor, typically greater than 500, is required on SCL if there are multiple masters on the bus, or if the master in a single-master system has an open-drain SCL output. Series resistors in line with SDA and SCL are optional. Series resistors protect the digital inputs of the MAX9850 from high-voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals. Bit Transfer One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period of the SCL pulse. Changes in SDA while SCL is high are control signals (see the START and STOP Conditions section). SDA and SCL idle high when the I2C bus is not busy. 29 ______________________________________________________________________________________ Stereo Audio DAC with DirectDrive Headphone Amplifier MAX9850 S Sr P Table 23. MAX9850 Address Map ADD MAX9850 SLAVE ADDRESS A6 0 0 A5 0 0 0 A4 1 1 1 A3 0 0 0 A2 0 0 0 A1 0 0 1 A0 0 1 1 R/W X X X SCL GND AVDD SDA SDA 0 X = Don't Care. Figure 6. START, STOP, and REPEATED START Conditions CLOCK PULSE FOR ACKNOWLEDGMENT START CONDITION SCL 1 2 8 NOT ACKNOWLEDGE 9 Slave Address The MAX9850 is programmable to one of three slave addresses (see Table 23). These slave addresses are unique device IDs. Connect ADD to GND, AVDD, or SDA to set the I 2 C slave address. The address is defined as the seven most significant bits (MSBs) followed by the Read/Write bit. Set the Read/Write bit to 1 to configure the MAX9850 to read mode. Set the Read/Write bit to 0 to configure the MAX9850 to write mode. The address is the first byte of information sent to the MAX9850 after the START condition. Acknowledge The acknowledge bit (ACK) is a clocked 9th bit that the MAX9850 uses to handshake receipt of each byte of data when in write mode (see Figure 7). The MAX9850 pulls down SDA during the entire master-generated 9th clock pulse if the previous byte is successfully received. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master may retry communication. The master pulls down SDA during the 9th clock cycle to acknowledge receipt of data when the MAX9850 is in read mode. An acknowledge is sent by the master after each read byte to allow data transfer to continue. A notacknowledge is sent when the master reads the final byte of data from the MAX9850, followed by a STOP condition. SDA ACKNOWLEDGE Figure 7. Acknowledge Start and Stop Conditions SDA and SCL idle high when the bus is not in use. A master initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA while SCL is high (Figure 6). A START condition from the master signals the beginning of a transmission to the MAX9850. The master terminates transmission, and frees the bus, by issuing a STOP condition. The bus remains active if a REPEATED START condition is generated instead of a STOP condition. Early STOP Conditions The MAX9850 recognizes a STOP condition at any point during data transmission except if the STOP condition occurs in the same high pulse as a START condition. For proper operation, do not send a STOP condition during the same SCL high pulse as the START condition. 30 ______________________________________________________________________________________ Stereo Audio DAC with DirectDrive Headphone Amplifier Write Data Format A write to the MAX9850 includes transmission of a START condition, the slave address with the R/W bit set to 0 (see Table 23), one byte of data to configure the internal register address pointer, one or more bytes of data, and a STOP condition. Figure 8 illustrates the proper frame format for writing one byte of data to the MAX9850. Figure 9 illustrates the frame format for writing n-bytes of data to the MAX9850. The slave address with the R/W bit set to 0 indicates that the master intends to write data to the MAX9850. The MAX9850 acknowledges receipt of the address byte during the master-generated 9th SCL pulse. The second byte transmitted from the master configures the MAX9850's internal register address pointer. The pointer tells the MAX9850 where to write the next byte of data. An acknowledge pulse is sent by the MAX9850 upon receipt of the address pointer data. The third byte sent to the MAX9850 contains the data that will be written to the chosen register. An acknowledge pulse from the MAX9850 signals receipt of the data byte. The address pointer autoincrements to the next register address after each received data byte. This autoincrement feature allows a master to write to sequential registers within one continuous frame. Figure 9 illustrates how to write to multiple registers with one frame. The master signals the end of transmission by issuing a STOP condition. Register addresses greater than 0xA are reserved. Do not write to these addresses. Read Data Format Send the slave address with the R/W bit set to 1 to initiate a read operation. The MAX9850 acknowledges receipt of its slave address by pulling SDA low during the 9th SCL clock pulse. A START command followed by a read command resets the address pointer to register 0x0. The first byte transmitted from the MAX9850 will be the contents of register 0x0. Transmitted data is valid on the rising edge of the master-generated serial clock (SCL). The address pointer autoincrements after each read data byte. This autoincrement feature allows all registers to be read sequentially within one continuous frame. A STOP condition can be issued after any number of read data bytes. If a STOP condition is issued followed by another read operation, the first data byte to be read will be from register 0x0 and subsequent reads will autoincrement the address pointer until the next STOP condition. MAX9850 ACKNOWLEDGE FROM MAX9850 B7 ACKNOWLEDGE FROM MAX9850 S SLAVE ADDRESS R/W 0 A ACKNOWLEDGE FROM MAX9850 REGISTER ADDRESS A DATA BYTE 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A P B6 B5 B4 B3 B2 B1 B0 Figure 8. Writing One Byte of Data to the MAX9850 NOT ACKNOWLEDGE FROM MASTER B7 B6 B5 B4 B3 B2 B1 B0 ACKNOWLEDGE FROM MAX9850 S SLAVE ADDRESS R/W 0 A ACKNOWLEDGE FROM MAX9850 REGISTER ADDRESS A Sr ACKNOWLEDGE FROM MAX9850 SLAVE ADDRESS R/W 1 A DATA BYTE 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A REPEATED START Figure 9. Writing n-Bytes of Data to the MAX9850 ______________________________________________________________________________________ 31 Stereo Audio DAC with DirectDrive Headphone Amplifier MAX9850 NOT ACKNOWLEDGE FROM MASTER B7 B6 B5 B4 B3 B2 B1 B0 ACKNOWLEDGE FROM MAX9850 S SLAVE ADDRESS R/W 0 A ACKNOWLEDGE FROM MAX9850 REGISTER ADDRESS A Sr ACKNOWLEDGE FROM MAX9850 SLAVE ADDRESS R/W 1 A DATA BYTE 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A P REPEATED START Figure 10. Reading One Byte of Data from MAX9850 ACKNOWLEDGE FROM MASTER B7 B6 B5 B4 B3 B2 B1 B0 ACKNOWLEDGE FROM MAX9850 S SLAVE ADDRESS R/W 0 A ACKNOWLEDGE FROM MAX9850 REGISTER ADDRESS A Sr ACKNOWLEDGE FROM MAX9850 SLAVE ADDRESS R/W 1 A FIRST DATA BYTE 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A NOT ACKNOWLEDGE FROM MASTER B7 B6 B5 B4 B3 B2 B1 B0 A P Nth DATA WORD 1 BYTE REPEATED START AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 11. Reading n-Bytes from MAX9850 The address pointer can be preset to a specific register before a read command is issued. The master presets the address pointer by first sending the MAX9850's slave address with the R/W bit set to 0 followed by the register address. A REPEATED START condition is then sent followed by the slave address with the R/W bit set to 1. The MAX9850 transmits the contents of the specified register. The address pointer autoincrements after transmitting the first byte. Attempting to read from register addresses higher than 0xB results in repeated reads of 0xB. Note that 0xB is a reserved register. The master acknowledges receipt of each read byte during the acknowledge clock pulse. The master must acknowledge all correctly received bytes except the last byte. The final byte must be followed by a notacknowledge from the master and then a STOP condition. Figure 10 illustrates the frame format for reading one byte from the MAX9850. Figure 11 illustrates the frame format for reading multiple bytes from the MAX9850. and B4). Setting the appropriate bits in the enable register will enable the desired circuit functions on the MAX9850. Finally, the global shutdown bit, SHDN needs to be set to 1 (register 0x5, bit B7). The enable bits can all be set with a single I2C write operation. It is good practice for an application to configure the I2C registers before taking the MAX9850 out of shutdown. This may include setting initial volume levels, DAC mode of operation, stereo or mono operation, and audio interface settings. Powering on the MAX9850 with all the registers set ensures that the audio output will not be interrupted. The charge pump starts and establishes the internal supply voltages once the appropriate byte is written to the enable register. The MAX9850 is ready for operation approximately 10ms after the charge pump is enabled. If selected, the headphone outputs will also complete a clickless/popless power-up sequence during this time. The headphone amplifier status bit (SHP) (register 0x1, bit B3) sets to 1 once the headphones are ready to operate. The line inputs and outputs will also turn on during this 10ms startup period if enabled. Let AC-coupling capacitors settle before enabling the line input amplifiers. The input-coupling capacitor charges to the output bias voltage of the driving device even while the MAX9850 is in shutdown. The input AC coupling capacitors are charged and ready for use immediately after power is applied to the system in most applications. Applications Information Powering On/Off the MAX9850 The MAX9850 powers on in low-power shutdown mode with the DAC, headphones, line inputs, and outputs all disabled. For useful circuit operation to be available, the charge pump needs to be activated using CPEN(1:0) in the enable register (register 0x5, bits B5 32 ______________________________________________________________________________________ Stereo Audio DAC with DirectDrive Headphone Amplifier MAX9850 1.8V TO 3.6V 1F 1F 1F 3.3V TO 5.5V 0.47F INL+ INL0.47F C SCL SDA REF 1F C1P DVDD PVDD AVDD OUTL VDD OUTR+ OUTR- MAX9850 OUTR DVDD C1N MCLK 0.47F INR+ INR10k GPIO HPL HPS HPR 0.47F MAX9701* OUTL+ OUTLSHDN PGND 0.47F DIGITAL AUDIO SOURCE SDIN BCLK LRCLK PVSS SVSS PGND DGND AGND 2.2F *FUTURE PRODUCT--CONTACT FACTORY FOR AVAILABILITY. Figure 12. Stereo Speakerphone The DAC begins its soft-start routine after being enabled and after receiving 32 LRCLK cycles. All internal filters are initialized and the DAC gain gradually ramps to maximum. The MAX9850's headphone output level is determined by the headphone amplifier volume setting. Mute the audio outputs before powering down the MAX9850 by setting MUTE to 1 (register 0x2, bit B7). Ramping the volume to its maximum attenuation is an alternative to muting the output. VMN in the status A register (register 0x0, bit B3) notifies the C when the outputs are at maximum attenuation. Disable the headphone and line outputs once the audio is fully attenuated. Headphone and line outputs can be disabled within 50s without any audible clicks or pops, once the audio is fully attenuated. Place the MAX9850 in shutdown after the outputs are disabled. Stereo Speakerphone The MAX9850 can be combined with a stereo speaker amplifier to create a complete speakerphone playback solution. The MAX9701, or another Maxim stereo speaker amplifier, can be used to drive the speakers while the MAX9850's integrated DirectDrive headphone amplifier drives the headphones (see Figure 12). Configure GPIO to output high when a headphone is not connected and low when the headphone is connected. Connect GPIO to the SHDN control of the MAX9701. Configure the interrupt enable register to set ALERT (register 0x0, bit B7) when HPS changes state. The C polls the status A register and waits for ALERT to set when HPS changes state. The C changes the state of GPIO when ALERT is set, either turning off the speaker amp because a headphone is connected or enabling the speaker amp when the headphone is disconnected. ______________________________________________________________________________________ 33 Stereo Audio DAC with DirectDrive Headphone Amplifier MAX9850 1.8V TO 3.6V 3.3V TO 5.5V 0.47F INL+ INL0.47F INL BASEBAND IC 0.47F INR DVDD PVDD AVDD OUTL OUTR DVDD REF C1P INR1F 0.47F C1N GPIO HPL HPS HPR SVSS PGND DGND AGND *FUTURE PRODUCT--CONTACT FACTORY FOR AVAILABILITY. 2.2F 0.47F 10k SHDN OUTLPGND 0.47F 0.47F INR+ 1F 1F 1F VDD OUTR+ OUTR- MAX9701* OUTL+ SCL SDA APPLICATIONS PROCESSOR MCLK SDIN BCLK LRCLK PVSS MAX9850 Figure 13. Cell Phone Audio Cell Phone Audio The MAX9850 is a complete cell-phone audio playback solution. In a typical application, ringtones are created and output through the application's processor on the digital audio bus. Connect the baseband IC to the line inputs of the MAX9850, INR and INL. The headphone amplifier outputs a summed version of the digital audio input and the line input (see Figure 13). The headphone amplifiers can provide almost 300mA per channel during a short-circuit event. The MAX9850 has been designed to withstand this current continuously. To avoid unnecessarily draining a battery, it is advised to enable the IOHR and IOHL hardware interrupt. The C can service the interrupt by disabling the headphone amplifiers and waiting for a timeout period. A headphone short-circuit event on the right channel only may also indicate that a mono headphone has been inserted into the stereo socket. The C can then automatically disable the right channel by placing the MAX9850 in mono mode. This resolves a mono jackinduced, short-circuit condition. PC Board Layout and Bypassing Proper layout and grounding are essential for optimum performance. Use large traces for the power-supply inputs and amplifier outputs to minimize losses due to parasitic trace resistance. Large traces also aid in moving heat away from the package. Proper grounding improves audio performance, minimizes crosstalk between channels, and prevents any switching noise from coupling into the audio signal. Connect PGND, DGND, and AGND together at a single point on the PC board. Route DGND, PGND, and all traces that carry switching transients or digital signals away from AGND and traces or components in the analog audio-signal path. Connect all components associated with the charge pump to PGND. Connect PVSS and SVSS together at the device. Place the charge-pump capacitors as close to PVSS as possible. Ensure C2 is connected to PGND. Bypass PV DD with 1F to PGND. Place the bypass capacitors as close to the device as possible. The MAX9850 thin QFN package features an exposed thermal pad on its underside. This pad lowers the package's thermal resistance by providing a direct heat conduction path from the die to the printed circuit board. If possible, connect the exposed thermal pad to an electrically isolated, large pad of copper. If it cannot be left floating, connect it to AGND. Headphone Short Circuit 34 ______________________________________________________________________________________ Stereo Audio DAC with DirectDrive Headphone Amplifier MAX9850 Pin Configuration PVDD PGND PVSS SDA SCL C1N C1P Chip Information TRANSISTOR COUNT: 104,069 PROCESS: BiCMOS TOP VIEW 28 LRCLK BCLK SDIN DVDD MCLK DGND ADD 27 26 25 24 23 22 21 20 19 HPS SVSS HPL HPR AVDD PREG NREG 1 2 3 4 5 6 7 8 GPIO MAX9850 18 17 16 15 9 INR 10 INL 11 OUTR 12 OUTL 13 REF 14 AGND TQFN ______________________________________________________________________________________ 35 Stereo Audio DAC with DirectDrive Headphone Amplifier MAX9850 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) QFN THIN.EPS L 0.15 C A D2 C L D D/2 0.15 C B b D2/2 0.10 M C A B k MARKING XXXXX E/2 E2/2 E (NE-1) X e C L E2 k L PIN # 1 I.D. DETAIL A e (ND-1) X e PIN # 1 I.D. 0.35x45 DETAIL B e L1 L C L C L L e 0.10 C A 0.08 C e C A1 A3 PACKAGE OUTLINE, 16, 20, 28, 32L THIN QFN, 5x5x0.8mm -DRAWING NOT TO SCALE- 21-0140 F 1 2 COMMON DIMENSIONS PKG. 16L 5x5 32L 5x5 20L 5x5 28L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. A A1 A3 b D E e k L L1 N ND NE JEDEC 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. PKG. CODES T1655-1 T1655-2 T1655N-1 T2055-2 T2055-3 T2055-4 T2055-5 T2855-1 T2855-2 T2855-3 T2855-4 T2855-5 T2855-6 T2855-7 T2855-8 T2855N-1 T3255-2 T3255-3 T3255-4 T3255N-1 EXPOSED PAD VARIATIONS D2 MIN. NOM. MAX. MIN. E2 NOM. MAX. L 0.15 DOWN BONDS ALLOWED 3.00 3.00 3.00 3.00 3.00 3.00 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00 3.10 3.20 3.10 3.20 3.10 3.20 3.10 3.10 3.10 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.20 3.20 3.20 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.80 BSC. 0.65 BSC. 0.50 BSC. 0.50 BSC. 0.25 - 0.25 - 0.25 - 0.25 0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 16 4 4 WHHB 20 5 5 WHHC 28 7 7 WHHD-1 32 8 8 WHHD-2 - ** ** ** ** ** ** 0.40 ** ** ** ** ** ** ** 0.40 ** ** ** ** ** NO YES NO NO YES NO Y NO NO YES YES NO NO YES Y N NO YES NO NO NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. ** SEE COMMON DIMENSIONS TABLE 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1, T2855-3 AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. 11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. PACKAGE OUTLINE, 16, 20, 28, 32L THIN QFN, 5x5x0.8mm -DRAWING NOT TO SCALE- 21-0140 F 2 2 MAX9850 Package Code: T2855-6 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 36 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. |
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